This drawing shows the second level of decoding. This panel is replicated on each of the four memory racks and takes the control signals provided by the first level decoder, along with bit 9 (F9) of the order, to select one of the final decoders. These are duplicated on each memory rack and are designated Up and Down.

The gates at the upper left portion perform this decoding generating four control signals DecUpOut, DecUpIn, DecDownOut and DecDownIn.

In addition, the panel also contains buffers and inverters:

At bottom left two buffers provide Main Input Bus (MIB) and Clock signals to each of the Memory Panels.

At upper right are eight inverters which invert the input gating signals (T0In - T7In) to close off the recirculation path in the Memory Panels when new data is being written to memory.

Finally, at bottom right is an eight-input wired-OR gate which merges and buffers the outputs from the Memory Panels to feed the Main Output Bus (MOB0).