Panel 3 of the CCU is concerned with shift orders. The Edsac shift instructions are strange in that the number of places shifted depends on the position of the least significant bit in the instruction.

The instruction is compared with Dy, which is emitted by the TCT and when there is a match, an end pulse EP2 is generated. This terminates the instruction. For left shifts, the maximum number of places is 13, while for a right shift you can do 15. In these cases, the terminating bit is the least significant bit of the opcode part of the instruction, and the address bits must all be zeros.

The output G5 goes to the Shifting Unit to enable the shifting logic.

The signal ResetFF10 is used to terminate the insertion of propagated sign bits.

The logic here is unchanged from the Report Figure 15, apart from minor adjustments to timing for the simulation.