This is the Accumulator Shifting Unit. This unit normally delays the output from the Accumulator to the Adder by two pulse intervals. When a shift operation is called for, it either inserts an extra delay, or bypasses the normal delay. This causes the number to be shifted left or right according to the instruction.

In the simulation, there is an additional delay due to propagation time through the gates, and so the output is gated with a clock pulse that has been delayed by 3 timesteps. All inputs to the Adder are delayed by this amount so that the input pulses will coincide correctly.