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Pull requests: amaranth-lang/amaranth-soc

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Pull requests list

Add annotations for memory maps, wishbone and CSR primitives [updated]

#104 opened Jul 30, 2025 by robtaylor

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[WIP] Add reference-level documentation

#82 opened Apr 9, 2024 by jfng • Draft

1

Implement RFC 60: UART peripheral.

#81 opened Mar 29, 2024 by jfng • Draft

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Add annotations for memory maps, wishbone and CSR primitives.

#58 opened Dec 5, 2023 by jfng

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8

wishbone.bus.Decoder: Only assert stb when slave is selected

#31 opened Aug 23, 2021 by antonblanchard

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2

csr/bus: Take data width into account for register writes

#30 opened May 14, 2021 by kbeckmann

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#29 opened Apr 20, 2021 by Fatsie

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CSR: Export Wishbone bridge from nmigen_soc.csr

#28 opened Apr 20, 2021 by Fatsie

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Make optional properties return None while uninitialized.

#26 opened Aug 22, 2020 by jfng

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1

[WIP]wishbone.Connector class

#21 opened Jul 1, 2020 by Fatsie

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35

csr.periph: add Peripheral base class.

#11 opened Mar 23, 2020 by jfng

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5

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