gnucap.git - Gnu Circuit Analysis Package

diff --git a/apps/c_ground.cc b/apps/c_ground.cc
index 2af88cb4..02679e7d 100644
--- a/apps/c_ground.cc
+++ b/apps/c_ground.cc

@@ -37,6 +37,8 @@ public:

assert(Scope);

assert(Scope->nodes());

std::string name;

+ std::string full;

+ full = "ground " + cmd.tail();

cmd >> name >> ";";

DEV_DOT* dd = new DEV_DOT;

dd->set_owner(nullptr);

@@ -46,7 +48,7 @@ public:

if(name == "0" && cmd.fullstring()[0]=='.'){ untested();

// spice

}else{

- dd->set(cmd.fullstring());

+ dd->set(full);

// TODO: lang_verilog get_identifier

if(name[0] == '\\'){

diff --git a/apps/lang_spice.cc b/apps/lang_spice.cc
index 0f7c1ae8..3d031d2d 100644
--- a/apps/lang_spice.cc
+++ b/apps/lang_spice.cc

@@ -774,6 +774,10 @@ void LANG_SPICE_BASE::print_comment(OMSTREAM& o, const DEV_COMMENT* x)

void LANG_SPICE_BASE::print_command(OMSTREAM& o, const DEV_DOT* x)

{itested();

assert(x);

+ if(x->s()[0] != '.'){

+ o << '.';

+ }else{

+ }

o << x->s() << '\n';

}

/*--------------------------------------------------------------------------*/

diff --git a/apps/lang_verilog.cc b/apps/lang_verilog.cc
index 8285374f..0fd554ca 100644
--- a/apps/lang_verilog.cc
+++ b/apps/lang_verilog.cc

@@ -31,6 +31,8 @@

/*--------------------------------------------------------------------------*/

namespace {

/*--------------------------------------------------------------------------*/

+static int nest;

+/*--------------------------------------------------------------------------*/

class LANG_VERILOG : public LANGUAGE {

enum MODE {mDEFAULT, mPARAMSET} _mode;

mutable int arg_count;

@@ -233,27 +235,14 @@ void LANG_VERILOG::parse_label(CS& cmd, CARD* x)

}

}

/*--------------------------------------------------------------------------*/

-// map to verilog representation

-std::string mangle(std::string const& name)

-{

- if(isdigit(name[0])) {

- return '\\' + name + " ";

- }else if(name[0] == '\\') {

- return name + " ";

- }else{

- // ok, for now.

- // probably need '\\' ... ' ' whenever special characters are used.

- return name;

- }

-}

-/*--------------------------------------------------------------------------*/

// get identifier and turn into internal representation

-// "1円 " -> "1" -- so it also works with spice

-// "\a " -> "a" -- identical, use simple form

-// "\$ " -> "\$" -- not sure

-// "\a* " -> "\a*" -- keep escaped string

-// "\\\ " -> "\\\" -- keep escaped string

-std::string get_identifier(CS& cmd, std::string const& term)

+// "1円 " -> "1" -- so it also works with spice

+// "\a " -> "a" -- identical, use simple form

+// "\$ " -> "$" -- not sure.

+// "\a* " -> "a*" -- store unprotected

+// "\\\xyz " -> "\xyz" -- remove additional escapes

+// "\foo\bar" -- incomplete

+static std::string get_identifier(CS& cmd, std::string const& term)

{

cmd.skipbl();

std::string id;

@@ -263,37 +252,68 @@ std::string get_identifier(CS& cmd, std::string const& term)

}else{

}

- if(cmd >> '\\') {

- id = cmd.get_to(" \t\f");

- trace1("got to", cmd.peek());

- cmd.skip();

+ bool esc = cmd.skip1('\\');

- {

- bool plain = true;

- for(size_t i = 0; plain && i<id.size() ; ++i) {

- if (isalnum(id[i])) {

- }else if (id[i] == '$') {

- plain = false;

- }else{

- plain = false;

- }

+ while(esc && cmd.more()) {

+ if(cmd.skip1('\\')){

+ if(cmd.skip1('\\')){

+ id += "\\";

+ }else{ untested();

+ cmd.warn(bDANGER, "invalid escaped char");

}

+ }else{

+ }

+ id += cmd.get_to(" \t\f\\");

- if(plain) {

- // don't touch, for now.

- }else{

- // store escaped string.

- id = "\\" + id;

- }

+ if(cmd.skip1(" \t\f")){

+ break;

+ }else{ untested();

}

- }else{

+ }

+

+ if(!esc) {

id = cmd.ctos(term, "", "");

+ }else{

}

trace1("identifier", id);

return id;

}

/*--------------------------------------------------------------------------*/

+void print_identifier(OMSTREAM& o, std::string const& name)

+{

+ bool plain = true;

+

+ if(isalpha(name[0])){

+ }else if(name[0] == '$'){

+ }else if(name[0] == '_'){ untested();

+ }else{

+ plain = false;

+ }

+

+ for(size_t i=1; plain && i<name.size(); ++i){

+ if(isalnum(name[i])){

+ }else if(name[i] == '_'){

+ }else{

+ plain = false;

+ }

+ }

+

+ if(plain){

+ o << name;

+ }else{

+ o << '\\';

+ for(size_t i=0; i<name.size(); ++i){

+ if(name[i] == '\\'){

+ o << '\\';

+ }else{

+ }

+ o << name[i];

+ }

+ o << ' ';

+ }

+}

+/*--------------------------------------------------------------------------*/

void LANG_VERILOG::parse_ports(CS& cmd, COMPONENT* x, bool all_new)

{

assert(x);

@@ -804,8 +824,14 @@ void LANG_VERILOG::print_args(OMSTREAM& o, const COMPONENT* x)

if (x->param_is_printable(ii)) {

o << sep;

print_attributes(o, x->param_id_tag(ii));

- o << '.' << x->param_name(ii) << '(' << x->param_value(ii) << ')';

- sep = ',';

+ std::string pn = x->param_name(ii);

+ if(pn==""){ untested();

+ o << x->param_value(ii);

+ sep = ", ";

+ }else{

+ o << '.' << x->param_name(ii) << '(' << x->param_value(ii) << ')';

+ sep = ',';

+ }

}else{

}

}

@@ -816,13 +842,13 @@ void LANG_VERILOG::print_args(OMSTREAM& o, const COMPONENT* x)

void LANG_VERILOG::print_type(OMSTREAM& o, const COMPONENT* x)

{

assert(x);

- o << x->dev_type();

+ print_identifier(o, x->dev_type());

}

/*--------------------------------------------------------------------------*/

void LANG_VERILOG::print_label(OMSTREAM& o, const COMPONENT* x)

{

assert(x);

- o << x->short_label();

+ print_identifier(o, x->short_label());

}

/*--------------------------------------------------------------------------*/

void LANG_VERILOG::print_ports_long(OMSTREAM& o, const COMPONENT* x)

@@ -836,8 +862,17 @@ void LANG_VERILOG::print_ports_long(OMSTREAM& o, const COMPONENT* x)

if(x->node_is_connected(ii)){

o << sep;

print_attributes(o, x->port_id_tag(ii));

- o << '.' << mangle(x->port_name(ii)) << '(' << mangle(x->port_value(ii)) << ')';

- sep = ',';

+ if(!x->port_name(ii).size()){

+ print_identifier(o, x->port_value(ii));

+ sep = ", ";

+ }else{

+ o << '.';

+ print_identifier(o, x->port_name(ii));

+ o << '(';

+ print_identifier(o, x->port_value(ii));

+ o << ')';

+ sep = ',';

+ }

}else{

}

}

@@ -885,10 +920,14 @@ void LANG_VERILOG::print_module(OMSTREAM& o, const BASE_SUBCKT* x)

print_ports_long(o, x);

o << ";\n";

+ ++nest;

for (CARD_LIST::const_iterator ci = x->subckt()->begin(); ci != x->subckt()->end(); ++ci) {

+ o << std::string(nest*2, ' ');

print_item(o, *ci);

}

+ --nest;

+ o << std::string(nest*2, ' ');

o << "endmodule // " << x->short_label() << "\n\n";

}

/*--------------------------------------------------------------------------*/

diff --git a/include/patchlev.h b/include/patchlev.h
index 0c77c270..e49e2f9d 100644
--- a/include/patchlev.h
+++ b/include/patchlev.h

@@ -1 +1 @@

-#define PATCHLEVEL "ctof 2025年10月31日"

+#define PATCHLEVEL "parse_dump 2025年11月11日"

diff --git a/lib/e_card.cc b/lib/e_card.cc
index 9178a7d3..0ca75d4d 100644
--- a/lib/e_card.cc
+++ b/lib/e_card.cc

@@ -188,31 +188,22 @@ CARD* CARD::find_in_my_scope(const std::string& name)

assert(scope());

CARD_LIST::iterator i = scope()->find_(name);

+ CARD_LIST::iterator j = i;

if (i == scope()->end()) {

throw Exception_Cant_Find(long_label(), name,

((owner()) ? owner()->long_label() : "(root)"));

+ }else if(scope()->find_again(name, ++j) != scope()->end()){

+ error(bWARNING, "duplicate match " + name + " in " + long_label() + "\n");

}else{

}

return *i;

}

/*--------------------------------------------------------------------------*/

-/* find_in_my_scope: find in same scope as myself

- * whatever is found will have the same owner as me.

- * capable of finding me.

- * throws exception if can't find.

+/* find_in_my_scope const. same as above, but const

*/

-const CARD* CARD::find_in_my_scope(const std::string& name)const

+const CARD* CARD::find_in_my_scope(const std::string& name) const

{

- assert(name != "");

- assert(scope());

-

- CARD_LIST::const_iterator i = scope()->find_(name);

- if (i == scope()->end()) {

- throw Exception_Cant_Find(long_label(), name,

- ((owner()) ? owner()->long_label() : "(root)"));

- }else{

- }

- return *i;

+ return const_cast<CARD*>(this)->find_in_my_scope(name);

}

/*--------------------------------------------------------------------------*/

/* find_in_parent_scope: find in parent's scope

@@ -227,8 +218,11 @@ const CARD* CARD::find_in_parent_scope(const std::string& name)const

const CARD_LIST* p_scope = (scope()->parent()) ? scope()->parent() : scope();

CARD_LIST::const_iterator i = p_scope->find_(name);

+ CARD_LIST::const_iterator j = i;

if (i == p_scope->end()) {

throw Exception_Cant_Find(long_label(), name);

+ }else if(p_scope->find_again(name, ++j) != p_scope->end()){

+ error(bWARNING, "duplicate match " + name + " in " + long_label() + "\n");

}else{

}

return *i;

diff --git a/tests/==out/c_ground.1.gc.out b/tests/==out/c_ground.1.gc.out
index bb352097..b5fe7335 100644
--- a/tests/==out/c_ground.1.gc.out
+++ b/tests/==out/c_ground.1.gc.out

@@ -1,6 +1,6 @@

module sink (.a(a));

ground gnd;

-resistor #(.r(1)) r (.p(gnd),.n(a));

+ resistor #(.r(1)) r (.p(gnd),.n(a));

endmodule // sink

ground gg

diff --git a/tests/==out/c_ground.2.gc.out b/tests/==out/c_ground.2.gc.out
index d43bcada..eb355656 100644
--- a/tests/==out/c_ground.2.gc.out
+++ b/tests/==out/c_ground.2.gc.out

@@ -3,7 +3,7 @@ endmodule // net

module sink (.a(a));

ground gnd;

-net #() n (.a(gnd),.b(a));

+ net #() n (.a(gnd),.b(a));

endmodule // sink

ground gg

diff --git a/tests/==out/d_cap.1.gc.out b/tests/==out/d_cap.1.gc.out
index 22a1d1d9..9d189baa 100644
--- a/tests/==out/d_cap.1.gc.out
+++ b/tests/==out/d_cap.1.gc.out

@@ -1,8 +1,8 @@

module m (.a(a),.b(b),.c(c));

ground 0円 ;

-capacitor #(.c(1),.$method("euleronly")) ca (.p(a),.n(0円 ));

-capacitor #(.c(1),.$method("traponly")) cb (.p(b),.n(0円 ));

-capacitor #(.c(1),.$method("euler")) cc (.p(c),.n(0円 ));

+ capacitor #(.c(1),.$method("euleronly")) ca (.p(a),.n(0円 ));

+ capacitor #(.c(1),.$method("traponly")) cb (.p(b),.n(0円 ));

+ capacitor #(.c(1),.$method("euler")) cc (.p(c),.n(0円 ));

endmodule // m

m #(.$method("traponly")) mm (.a(a),.b(b),.c(c));

diff --git a/tests/==out/d_cap.2.gc.out b/tests/==out/d_cap.2.gc.out
index 2a1d3be7..cb72c1e6 100644
--- a/tests/==out/d_cap.2.gc.out
+++ b/tests/==out/d_cap.2.gc.out

@@ -1,8 +1,8 @@

module m (.a(a),.b(b),.c(c));

ground 0円 ;

-capacitor #(.c(1),.$xposition(2),.$method("euler")) ca (.p(a),.n(0円 ));

-capacitor #(.c(1),.$method("euleronly")) cb (.p(b),.n(0円 ));

-capacitor #(.c(1),.$method("trap")) cc (.p(c),.n(0円 ));

+ capacitor #(.c(1),.$xposition(2),.$method("euler")) ca (.p(a),.n(0円 ));

+ capacitor #(.c(1),.$method("euleronly")) cb (.p(b),.n(0円 ));

+ capacitor #(.c(1),.$method("trap")) cc (.p(c),.n(0円 ));

endmodule // m

m #(.$method("traponly")) mm (.a(a),.b(b),.c(c));

diff --git a/tests/==out/d_diode.wrap.gc.out b/tests/==out/d_diode.wrap.gc.out
index 4fe2b36b..1b6cfc6f 100644
--- a/tests/==out/d_diode.wrap.gc.out
+++ b/tests/==out/d_diode.wrap.gc.out

@@ -1,15 +1,15 @@

module spice_diode (.1円 (1円 ),.2円 (2円 ));

-paramset mydiode d;

+ paramset mydiode d;

.tnom=NA( 27.); .is=Is; .rs=rs; .n=N; .tt=tt; .cjo=cjo; .pb=vj; .mj=M; .egap=NA( 1.11); .xti=NA( 3.); .fc=NA( 0.5);

endparamset

-mydiode #(.area(area)) D1 (.a(1円 ),.c(2円 ));

+ mydiode #(.area(area)) D1 (.a(1円 ),.c(2円 ));

endmodule // spice_diode

// TODO: this is actually a paramset

module Diode (.1円 (1円 ),.2円 (2円 ));

-// // ignored, but somehow used in .net files revisit later.

-spice_diode #(.area(Area),.Is(Is),.rs(Rs),.N(N),.cjo(Cj0),.vj(Vj),.M(M),.tt(Tt)) d1 (.1円 (2円 ),.2円 (1円 ));

+ // // ignored, but somehow used in .net files revisit later.

+ spice_diode #(.area(Area),.Is(Is),.rs(Rs),.N(N),.cjo(Cj0),.vj(Vj),.M(M),.tt(Tt)) d1 (.1円 (2円 ),.2円 (1円 ));

endmodule // Diode

# v(1) v(2)

diff --git a/tests/==out/d_logic.0.gc.out b/tests/==out/d_logic.0.gc.out
index 2dc79c40..f40afa19 100644
--- a/tests/==out/d_logic.0.gc.out
+++ b/tests/==out/d_logic.0.gc.out

@@ -3,24 +3,24 @@ paramset logic logic;

endparamset

module logic_test (.all(all),.out3(out3),.out2(out2),.out1(out1),.out0(out0),.in(in));

-inv #(.delay(1)) b0 (.out(out0),.in1(in));

-inv #(.delay(2)) b1 (.out(out1),.in1(in));

-inv #(.delay(3)) b2 (.out(out2),.in1(in));

-inv #(.delay(4)) b3 (.out(out3),.in1(in));

-nand #(.delay(1)) a (.out(all),.in1(out0),.in2(out1),.in3(out2),.in4(out3));

+ inv #(.delay(1)) b0 (.out(out0),.in1(in));

+ inv #(.delay(2)) b1 (.out(out1),.in1(in));

+ inv #(.delay(3)) b2 (.out(out2),.in1(in));

+ inv #(.delay(4)) b3 (.out(out3),.in1(in));

+ nand #(.delay(1)) a (.out(all),.in1(out0),.in2(out1),.in3(out2),.in4(out3));

endmodule // logic_test

module clock (.out(i0),.en(en));

-nand #(.delay(5)) i0 (.out(i0),.in1(i4),.in2(en));

-inv #(.delay(5)) i0 (.out(i4),.in1(i3));

-inv #(.delay(5)) i0 (.out(i3),.in1(i2));

-inv #(.delay(5)) i0 (.out(i2),.in1(i1));

-inv #(.delay(5)) i0 (.out(i1),.in1(i0));

+ nand #(.delay(5)) i0 (.out(i0),.in1(i4),.in2(en));

+ inv #(.delay(5)) i0 (.out(i4),.in1(i3));

+ inv #(.delay(5)) i0 (.out(i3),.in1(i2));

+ inv #(.delay(5)) i0 (.out(i2),.in1(i1));

+ inv #(.delay(5)) i0 (.out(i1),.in1(i0));

endmodule // clock

module main (.all(all),.out3(out3),.out2(out2),.out1(out1),.out0(out0),.en(en));

-logic_test #() t1 (.all(all),.out3(out3),.out2(out2),.out1(out1),.out0(out0),.in(clk));

-clock #() c1 (.out(clk),.en(en));

+ logic_test #() t1 (.all(all),.out3(out3),.out2(out2),.out1(out1),.out0(out0),.in(clk));

+ clock #() c1 (.out(clk),.en(en));

endmodule // main

m.t1.b0: can't find subckt: logicinv1, forcing digital

diff --git a/tests/==out/d_logic.2.gc.out b/tests/==out/d_logic.2.gc.out
index 79ac4319..3f24e6bc 100644
--- a/tests/==out/d_logic.2.gc.out
+++ b/tests/==out/d_logic.2.gc.out

@@ -37,9 +37,9 @@ inv #(.model(mos)) U5 (.out(5円 ),.in1(4円 ));

inv #(.model(mos)) U6 (.out(6円 ),.in1(5円 ));

inv #(.model(mos)) U7 (.out(7円 ),.in1(6円 ));

module mosinv1 (.2円 (2円 ),.3円 (3円 ));

-vsource #( DC 5.) Vdd (.p(1円 ),.n(0円 ));

-nmos #(.l(100.u),.w(100.u),.nrd(1.),.nrs(1.)) M1 (.d(2円 ),.g(3円 ),.s(0円 ),.b(0円 ));

-pmos #(.l(100.u),.w(100.u),.nrd(1.),.nrs(1.)) M2 (.d(2円 ),.g(3円 ),.s(1円 ),.b(1円 ));

+ vsource #( DC 5.) Vdd (.p(1円 ),.n(0円 ));

+ nmos #(.l(100.u),.w(100.u),.nrd(1.),.nrs(1.)) M1 (.d(2円 ),.g(3円 ),.s(0円 ),.b(0円 ));

+ pmos #(.l(100.u),.w(100.u),.nrd(1.),.nrs(1.)) M2 (.d(2円 ),.g(3円 ),.s(1円 ),.b(1円 ));

endmodule // mosinv1

//*+ends mosinv1

diff --git a/tests/==out/d_logic.dt.0.gc.out b/tests/==out/d_logic.dt.0.gc.out
index f5f56e0d..287cbbb3 100644
--- a/tests/==out/d_logic.dt.0.gc.out
+++ b/tests/==out/d_logic.dt.0.gc.out

@@ -1,7 +1,7 @@

inv #(.model(dummy_tmp)) (.out(a), .in1(b));

^ ? label required

module test (.a(a),.b(b));

-inv #(.model(dummy_tmp)) U_unnamed (.out(a),.in1(b));

+ inv #(.model(dummy_tmp)) U_unnamed (.out(a),.in1(b));

endmodule // test

paramset dummy_tmp logic;

diff --git a/tests/==out/d_net.1.gc.out b/tests/==out/d_net.1.gc.out
index 63be0c40..518f1506 100644
--- a/tests/==out/d_net.1.gc.out
+++ b/tests/==out/d_net.1.gc.out

@@ -8,9 +8,9 @@ endmodule // net

module main ();

ground 0円 ;

-resistor #(.r(1)) r (.p(n),.n(0円 ));

-isource #(.dc(1)) i (.p(0円 ),.n(m));

-net #() n1 (.a(n),.b(m));

+ resistor #(.r(1)) r (.p(n),.n(0円 ));

+ isource #(.dc(1)) i (.p(0円 ),.n(m));

+ net #() n1 (.a(n),.b(m));

endmodule // main

main #() m ();

diff --git a/tests/==out/d_subckt.02.gc.out b/tests/==out/d_subckt.02.gc.out
index ed5e39d4..f4e6d50e 100644
--- a/tests/==out/d_subckt.02.gc.out
+++ b/tests/==out/d_subckt.02.gc.out

@@ -1,9 +1,9 @@

module r (.a(a),.b(b));

-resistor #(.r(x+y)) r1 (.p(a),.n(b));

+ resistor #(.r(x+y)) r1 (.p(a),.n(b));

endmodule // r

module rr (.a(a),.b(b));

-r #(.x(x/3)) r0 (.a(a),.b(b));

+ r #(.x(x/3)) r0 (.a(a),.b(b));

endmodule // rr

vsource #(.dc(1)) v1 (.p(1円 ),.n(0円 ));

@@ -15,11 +15,11 @@ rr #(.x(6.1)) s3 (.a(1円 ),.b(0円 ));

27. 0.99998 2. 2. 2. 3.

vsource #(.dc(1)) v1 (.p(1円 ),.n(0円 ));

module r (.1円 (1円 ),.2円 (2円 ));

-resistor #(X+Y) R1 (.p(1円 ),.n(2円 ));

+ resistor #(X+Y) R1 (.p(1円 ),.n(2円 ));

endmodule // r

module rr (.1円 (1円 ),.2円 (2円 ));

-r #(.X(X/3)) X0 (.(1円 ),.(2円 ));

+ r #(.X(X/3)) X0 (1円 , 2円 );

endmodule // rr

rr #() s0 (.1円 (1円 ),.2円 (0円 ));

diff --git a/tests/==out/d_subckt.1.gc.out b/tests/==out/d_subckt.1.gc.out
index 13088926..b355e5d5 100644
--- a/tests/==out/d_subckt.1.gc.out
+++ b/tests/==out/d_subckt.1.gc.out

@@ -1,5 +1,5 @@

module r (.p(p),.n(n));

-resistor #(.r(1),.$mfactor(5)) r (.p(p),.n(n));

+ resistor #(.r(1),.$mfactor(5)) r (.p(p),.n(n));

endmodule // r

# v(1)

diff --git a/tests/==out/d_subckt.3.gc.out b/tests/==out/d_subckt.3.gc.out
index 159dbc77..5b4d6669 100644
--- a/tests/==out/d_subckt.3.gc.out
+++ b/tests/==out/d_subckt.3.gc.out

@@ -13,7 +13,7 @@ V1 ( 2 0 ) DC 1.

X1 ( 2 1 3 ) zzz

X2 ( 2 4 5 ) zzz

.subckt zzz ( 1 2 4 )

- ground 0円 ;

+.ground 0円 ;

R1 ( 1 2 ) 1.

R2 ( 2 0 ) 1.

R3 ( 2 3 ) 1.

diff --git a/tests/==out/d_subckt.4.gc.out b/tests/==out/d_subckt.4.gc.out
index 20b442c1..87d096a0 100644
--- a/tests/==out/d_subckt.4.gc.out
+++ b/tests/==out/d_subckt.4.gc.out

@@ -1,8 +1,8 @@

module main (.1円 (1円 ),.b(2円 ));

-// global 0円 ;

-resistor #(.r(1)) r1 (.p(1円 ),.n(2円 ));

-resistor #(.r(1)) r2 (.p(2円 ),.n(0円 ));

-isource #(.dc(1)) i1 (.p(0円 ),.n(1円 ));

+ // global 0円 ;

+ resistor #(.r(1)) r1 (.p(1円 ),.n(2円 ));

+ resistor #(.r(1)) r2 (.p(2円 ),.n(0円 ));

+ isource #(.dc(1)) i1 (.p(0円 ),.n(1円 ));

endmodule // main

main #() m (.1円 (1円 ));

@@ -16,10 +16,10 @@ transient timesteps: accepted=0, rejected=0, total=0

nodes: user=1, subckt=1, model=0, total=2

dctran density=50.0%, ac density=50.0%

module main (.1円 (1円 ),.b(2円 ));

-// global 0円 ;

-resistor #(.r(1)) r1 (.p(1円 ),.n(2円 ));

-resistor #(.r(1)) r2 (.p(2円 ),.n(0円 ));

-isource #(.dc(1)) i1 (.p(0円 ),.n(1円 ));

+ // global 0円 ;

+ resistor #(.r(1)) r1 (.p(1円 ),.n(2円 ));

+ resistor #(.r(1)) r2 (.p(2円 ),.n(0円 ));

+ isource #(.dc(1)) i1 (.p(0円 ),.n(1円 ));

endmodule // main

main #() m (.1円 (1円 ),.b(0円 ));

diff --git a/tests/==out/d_subckt.bin.0.ckt.out b/tests/==out/d_subckt.bin.0.ckt.out
new file mode 100644
index 00000000..17d61bd8
--- /dev/null
+++ b/tests/==out/d_subckt.bin.0.ckt.out

@@ -0,0 +1,9 @@

+* subckt, param, bin test

+>>>>>.subckt foo (a k)

+>>>>>.model mydio d is=1e-9

+>>>>>.model mydio d is=1e-10

+>>>>>.print op v(nodes)

+duplicate match mydio in x9.d1

+>>>>>.op

+# v(9)

+ 27. 0.53599

diff --git a/tests/==out/d_subckt.error.2.gc.out b/tests/==out/d_subckt.error.2.gc.out
index addcd84b..86ab280d 100644
--- a/tests/==out/d_subckt.error.2.gc.out
+++ b/tests/==out/d_subckt.error.2.gc.out

@@ -3,9 +3,9 @@ m #() mm(.a(1円 ), .b(0円 ));

m #() mm(.x(1円 ), .d(0円 ));

^ ? mm: mismatch x ignored

module m (.a(a),.d(d));

-resistor #(.r(1)) r0 (.p(a),.n(b));

-resistor #(.r(1)) r1 (.p(b),.n(c));

-resistor #(.r(1)) r2 (.p(c),.n(d));

+ resistor #(.r(1)) r0 (.p(a),.n(b));

+ resistor #(.r(1)) r1 (.p(b),.n(c));

+ resistor #(.r(1)) r2 (.p(c),.n(d));

endmodule // m

m #() mm (.a(1円 ));

diff --git a/tests/==out/d_subckt.idx0.gc.out b/tests/==out/d_subckt.idx0.gc.out
index c3a2bee8..7974edeb 100644
--- a/tests/==out/d_subckt.idx0.gc.out
+++ b/tests/==out/d_subckt.idx0.gc.out

@@ -1,5 +1,5 @@

module main (.a(a),.b(b));

-vsource #(.dc(x+z)) i1 (.p(a),.n(b));

+ vsource #(.dc(x+z)) i1 (.p(a),.n(b));

endmodule // main

ground gnd;

diff --git a/tests/==out/insensitive.0.gc.out b/tests/==out/insensitive.0.gc.out
index 1120ff97..24ac321a 100644
--- a/tests/==out/insensitive.0.gc.out
+++ b/tests/==out/insensitive.0.gc.out

@@ -1,15 +1,15 @@

\\ ground 0円

^ ? \\: no match

module aaa (.1円 (1円 ),.2円 (2円 ));

-vsource #(.dc(0)) vs (.p(1円 ),.n(2円 ));

+ vsource #(.dc(0)) vs (.p(1円 ),.n(2円 ));

endmodule // aaa

module AAA (.1円 (1円 ),.2円 (2円 ));

-vsource #(.dc(1)) vs (.p(1円 ),.n(2円 ));

+ vsource #(.dc(1)) vs (.p(1円 ),.n(2円 ));

endmodule // AAA

module bbb (.1円 (1円 ),.2円 (2円 ));

-AAA #() vs (.1円 (1円 ),.2円 (2円 ));

+ AAA #() vs (.1円 (1円 ),.2円 (2円 ));

endmodule // bbb

bbb #() b (.1円 (1円 ),.2円 (0円 ));

diff --git a/tests/==out/lang_verilog.0.gc.out b/tests/==out/lang_verilog.0.gc.out
index 0443a7a7..a519b4a8 100644
--- a/tests/==out/lang_verilog.0.gc.out
+++ b/tests/==out/lang_verilog.0.gc.out

@@ -1,8 +1,8 @@

resistor #(.r(1)) Rin2 (.p(a),.n(b));

resistor #(.r(1)) Rin2 (.p(a),.n(b));

resistor #(.r(1)) Rin2 (.p(\a*a ),.n(\-- ));

-resistor #(.r(1)) Rin2 (.p(\$aa ),.n(\\\ ));

+resistor #(.r(1)) Rin2 (.p($aa),.n(\\\ ));

Rin2 ( a b ) 1

Rin2 ( a b ) 1

-Rin2 ( \a*a \-- ) 1

-Rin2 ( \$aa \\\ ) 1

+Rin2 ( a*a -- ) 1

+Rin2 ( $aa \ ) 1

diff --git a/tests/==out/lang_verilog.0i.gc.out b/tests/==out/lang_verilog.0i.gc.out
index 5abe0b72..348ccc6b 100644
--- a/tests/==out/lang_verilog.0i.gc.out
+++ b/tests/==out/lang_verilog.0i.gc.out

@@ -1,7 +1,7 @@

# v(1)

27. 21.

module foo (.a(a),.b(b));

-vsource #(.dc(j)) v (.p(a),.n(b));

+ vsource #(.dc(j)) v (.p(a),.n(b));

endmodule // foo

foo #(.i(19),.a(2)) f (.a(1円 ),.b(0円 ));

diff --git a/tests/==out/lang_verilog.1.gc.out b/tests/==out/lang_verilog.1.gc.out
index 3f72c1fb..46a09779 100644
--- a/tests/==out/lang_verilog.1.gc.out
+++ b/tests/==out/lang_verilog.1.gc.out

@@ -3,20 +3,20 @@ paramset zz npn;

endparamset

module dumb_resistor (.a(a),.b(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-ground 0円 ;

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c),.n(out));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

+ ground 0円 ;

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c),.n(out));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.1a.gc.out b/tests/==out/lang_verilog.1a.gc.out
index c30f2885..aac71db7 100644
--- a/tests/==out/lang_verilog.1a.gc.out
+++ b/tests/==out/lang_verilog.1a.gc.out

@@ -5,20 +5,20 @@ paramset zz npn;

endparamset

module dumb_resistor (.a(a),.b(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-ground 0円 ;

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c),.n(out));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

+ ground 0円 ;

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c),.n(out));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.1b.gc.out b/tests/==out/lang_verilog.1b.gc.out
index cc930d51..0ef3ec57 100644
--- a/tests/==out/lang_verilog.1b.gc.out
+++ b/tests/==out/lang_verilog.1b.gc.out

@@ -4,20 +4,20 @@ paramset zz npn;

endparamset

module dumb_resistor (.aa(a),.bb(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-ground 0円 ;

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.aa(e),.bb(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.aa(b),.bb(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c),.n(out));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

+ ground 0円 ;

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.aa(e),.bb(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.aa(b),.bb(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c),.n(out));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.2.gc.out b/tests/==out/lang_verilog.2.gc.out
index e5d2972d..d6f18ec0 100644
--- a/tests/==out/lang_verilog.2.gc.out
+++ b/tests/==out/lang_verilog.2.gc.out

@@ -12,20 +12,20 @@ paramset zz npn;

endparamset

module dumb_resistor (.a(a),.b(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-// ground 0 // todo

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out));

+ // ground 0 // todo

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.2a.gc.out b/tests/==out/lang_verilog.2a.gc.out
index 99dcb5d7..75e88929 100644
--- a/tests/==out/lang_verilog.2a.gc.out
+++ b/tests/==out/lang_verilog.2a.gc.out

@@ -1,5 +1,5 @@

module foo (.a(a),.b(b));

-resistor #(.r(1.)) R (.p(a),.n(b));

+ resistor #(.r(1.)) R (.p(a),.n(b));

endmodule // foo

foo #() X1 (.b(b));

diff --git a/tests/==out/lang_verilog.3.gc.out b/tests/==out/lang_verilog.3.gc.out
index 423cf8f8..0a64033e 100644
--- a/tests/==out/lang_verilog.3.gc.out
+++ b/tests/==out/lang_verilog.3.gc.out

@@ -3,20 +3,20 @@ paramset zz npn;

endparamset

module dumb_resistor (.a(a),.b(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-ground 0円 ;

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c),.n(out));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

+ ground 0円 ;

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c),.n(out));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out),.n(0円 ));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.4.gc.out b/tests/==out/lang_verilog.4.gc.out
index 9c75e445..e864d697 100644
--- a/tests/==out/lang_verilog.4.gc.out
+++ b/tests/==out/lang_verilog.4.gc.out

@@ -1,4 +1,4 @@

module rr (.a(a),.b(b),.c(c),.ref(ref));

-resistor #(.r($temperature())) r (.p(b),.n(ref));

+ resistor #(.r($temperature())) r (.p(b),.n(ref));

endmodule // rr

diff --git a/tests/==out/lang_verilog.5.gc.out b/tests/==out/lang_verilog.5.gc.out
index c89f9f21..4c340c53 100644
--- a/tests/==out/lang_verilog.5.gc.out
+++ b/tests/==out/lang_verilog.5.gc.out

@@ -1,10 +1,10 @@

wireww; // no match

^ ? wireww: no match

module test (.p(x),.q(y));

- electrical x, y;

- inout x;

- inout y;

- wire w;

-resistor #() r1 (.p(a),.n(b));

+ electrical x, y;

+ inout x;

+ inout y;

+ wire w;

+ resistor #() r1 (.p(a),.n(b));

endmodule // test

diff --git a/tests/==out/lang_verilog.dup.0.gc.out b/tests/==out/lang_verilog.dup.0.gc.out
new file mode 100644
index 00000000..27201ee5
--- /dev/null
+++ b/tests/==out/lang_verilog.dup.0.gc.out

@@ -0,0 +1,10 @@

+ r2 #(.r(300)) r2(a,b);

+ ^ ? aaa.r2: already set r, ignored

+module aaa (.a(a),.b(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ resistor #(.r(100)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r2 (.p(a),.n(b));

+endmodule // aaa

+

+# v(a)

+ 0. 33.333

diff --git a/tests/==out/lang_verilog.dup.1.gc.out b/tests/==out/lang_verilog.dup.1.gc.out
new file mode 100644
index 00000000..ca9eb95a
--- /dev/null
+++ b/tests/==out/lang_verilog.dup.1.gc.out

@@ -0,0 +1,15 @@

+duplicate match bbb in aaa

+module aaa (.a(a),.b(b));

+ module bbb (.a(a),.b(b));

+ resistor #(.r(1)) r1 (.p(a),.n(b));

+ endmodule // bbb

+

+ module bbb (.a(a),.b(b));

+ resistor #(.r(2)) r1 (.p(a),.n(b));

+ endmodule // bbb

+

+ bbb #() r2 (.a(a),.b(b));

+endmodule // aaa

+

+# v(a)

+ 0. 1.

diff --git a/tests/==out/lang_verilog.error.2.gc.out b/tests/==out/lang_verilog.error.2.gc.out
index 14bb2094..3dd8afbd 100644
--- a/tests/==out/lang_verilog.error.2.gc.out
+++ b/tests/==out/lang_verilog.error.2.gc.out

@@ -15,8 +15,8 @@ vccs #(.gm({alpha*adap}))) iF(0 f cd 0);

crash(x, y);

^ ? label required

module crash (.iout(iout),.nC(nC));

-// extra paren in vccs

-vccs #(.gm({alpha*adap})) G_unnamed (.sink(?????),.src(?????),.ps(?????),.ns(?????));

+ // extra paren in vccs

+ vccs #(.gm({alpha*adap})) G_unnamed (.sink(\????? ),.src(\????? ),.ps(\????? ),.ns(\????? ));

endmodule // crash

// syntax error, no label

diff --git a/tests/==out/lang_verilog.error.3.gc.out b/tests/==out/lang_verilog.error.3.gc.out
index 429fac45..570c906c 100644
--- a/tests/==out/lang_verilog.error.3.gc.out
+++ b/tests/==out/lang_verilog.error.3.gc.out

@@ -13,7 +13,7 @@ vccs #(.gm({alpha*adap}))) iF(0 f cd 0);

vccs #(.gm({alpha*adap}))) iF(0 f cd 0);

^ ? what's this?

// error .. extra paren, rest of line not parsed

-vccs #(.gm({alpha*adap})) G_unnamed (.sink(?????),.src(?????),.ps(?????),.ns(?????));

+vccs #(.gm({alpha*adap})) G_unnamed (.sink(\????? ),.src(\????? ),.ps(\????? ),.ns(\????? ));

print tran v(x) v(y)

^ ? no match

print tran v(x) v(y)

diff --git a/tests/==out/lang_verilog.error.7.gc.out b/tests/==out/lang_verilog.error.7.gc.out
index 066e17a8..c3d9bcf0 100644
--- a/tests/==out/lang_verilog.error.7.gc.out
+++ b/tests/==out/lang_verilog.error.7.gc.out

@@ -11,19 +11,19 @@ paramset zz npn;

endparamset

module dumb_resistor (.a(a),.b(b));

-resistor #(.r(r)) R1 (.p(a),.n(b));

+ resistor #(.r(r)) R1 (.p(a),.n(b));

endmodule // dumb_resistor

module foo (.vcc(vcc),.in(in),.out(out));

-resistor #(.r(z)) Rc (.p(c),.n(vcc));

-zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

-dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

-resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

-dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

-capacitor #(.c(1u)) Cin (.p(b),.n(in));

-capacitor #(.c(1u)) Cout (.p(c));

-resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

-resistor #(.r(100k)) Rout (.p(out));

+ resistor #(.r(z)) Rc (.p(c),.n(vcc));

+ zz #(.area(NA( 1.))) q1 (.c(c),.b(b),.e(e));

+ dumb_resistor #(.r(abs(-z)/10)) Re (.a(e),.b(0円 ));

+ resistor #(.r(100k)) Rb1 (.p(b),.n(vcc));

+ dumb_resistor #(.r(r)) Rb2 (.a(b),.b(0円 ));

+ capacitor #(.c(1u)) Cin (.p(b),.n(in));

+ capacitor #(.c(1u)) Cout (.p(c));

+ resistor #(.r(100k)) Rin (.p(in),.n(0円 ));

+ resistor #(.r(100k)) Rout (.p(out));

endmodule // foo

foo #(.r(10k)) X1 (.vcc(V_cc),.in(amp_in),.out(out));

diff --git a/tests/==out/lang_verilog.error.8.gc.out b/tests/==out/lang_verilog.error.8.gc.out
index 99d9f762..367b1c65 100644
--- a/tests/==out/lang_verilog.error.8.gc.out
+++ b/tests/==out/lang_verilog.error.8.gc.out

@@ -1,9 +1,9 @@

module bbb (.a(a),.f(f));

-vsource #(.dc(1.)) v1 (.p(a),.n(f));

+ vsource #(.dc(1.)) v1 (.p(a),.n(f));

endmodule // bbb

module aaa (.a(a),.f(f));

-bbb #() tt ();

+ bbb #() tt ();

endmodule // aaa

aaa #() bug (.a(a),.f(b));

diff --git a/tests/==out/m_expr.error.0a.gc.out b/tests/==out/m_expr.error.0a.gc.out
index 2d87b94c..90012227 100644
--- a/tests/==out/m_expr.error.0a.gc.out
+++ b/tests/==out/m_expr.error.0a.gc.out

@@ -15,7 +15,7 @@ capacitor #(" <test> + 4 ") r1(1円 , 0円 );

"list"

capacitor #(.c(a3)) r1 (.p(1円 ),.n(0円 ));

capacitor #(.c(<aaa>)) r1 (.p(1円 ),.n(0円 ));

-capacitor #() <test> + 4 (.p(?????),.n(?????));

+capacitor #() \ <test> + 4 (.p(\????? ),.n(\????? ));

"dc"

parameter <test> not specified, using default

parameter <test> value is "NOT_INPUT"

diff --git a/tests/==out/net.0.gc.out b/tests/==out/net.0.gc.out
index cb2e8a56..55d2c34a 100644
--- a/tests/==out/net.0.gc.out
+++ b/tests/==out/net.0.gc.out

@@ -2,11 +2,11 @@ module net (.a(i),.b(i));

endmodule // net

module main ();

-ground 0円 ;

-resistor #(.r(1.)) r1 (.p(2円 ),.n(0円 ));

-net #() n1 (.a(1円 ),.b(3円 ));

-net #() n2 (.a(3円 ),.b(2円 ));

-vsource #(.dc(1.)) v1 (.p(1円 ),.n(0円 ));

+ ground 0円 ;

+ resistor #(.r(1.)) r1 (.p(2円 ),.n(0円 ));

+ net #() n1 (.a(1円 ),.b(3円 ));

+ net #() n2 (.a(3円 ),.b(2円 ));

+ vsource #(.dc(1.)) v1 (.p(1円 ),.n(0円 ));

endmodule // main

# i(Xm.r1)

diff --git a/tests/==out/net.0a.gc.out b/tests/==out/net.0a.gc.out
index 826a44ac..f5b59f72 100644
--- a/tests/==out/net.0a.gc.out
+++ b/tests/==out/net.0a.gc.out

@@ -2,10 +2,10 @@ module net (.a(i),.b(i),.c(j),.d(j));

endmodule // net

module main ();

-ground g;

-resistor #(.r(1.)) r1 (.p(2円 ),.n(g));

-net #() n1 (.a(1円 ),.b(2円 ),.c(4円 ),.d(g));

-vsource #(.dc(1.)) v1 (.p(1円 ),.n(4円 ));

+ ground g;

+ resistor #(.r(1.)) r1 (.p(2円 ),.n(g));

+ net #() n1 (.a(1円 ),.b(2円 ),.c(4円 ),.d(g));

+ vsource #(.dc(1.)) v1 (.p(1円 ),.n(4円 ));

endmodule // main

# i(Xm.r1)

diff --git a/tests/==out/u_attrib.0.gc.out b/tests/==out/u_attrib.0.gc.out
index d5e56432..88496264 100644
--- a/tests/==out/u_attrib.0.gc.out
+++ b/tests/==out/u_attrib.0.gc.out

@@ -12,6 +12,6 @@ module aaa (.c(c),.d(d));

endmodule // aaa

module bbb (.e(e),.f(f));

-aaa #((* x *) .x(1),(* a *) .a(2),(* b *) .b(3),(* y *) .y(4)) a1 (.c(a),.d(b));

+ aaa #((* x *) .x(1),(* a *) .a(2),(* b *) .b(3),(* y *) .y(4)) a1 (.c(a),.d(b));

endmodule // bbb

diff --git a/tests/==out/u_attrib.1.gc.out b/tests/==out/u_attrib.1.gc.out
index 6c5262c3..dee9c7ab 100644
--- a/tests/==out/u_attrib.1.gc.out
+++ b/tests/==out/u_attrib.1.gc.out

@@ -27,29 +27,29 @@

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

diff --git a/tests/==out/u_attrib.2.gc.out b/tests/==out/u_attrib.2.gc.out
index 8e1e9bf2..6d24ecec 100644
--- a/tests/==out/u_attrib.2.gc.out
+++ b/tests/==out/u_attrib.2.gc.out

@@ -26,26 +26,26 @@

" "

"list"

module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-resistor #((* r *) .r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-resistor #(.r(100)) r5 (.p(a),.n(b));

-resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ resistor #((* r *) .r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ resistor #(.r(100)) r5 (.p(a),.n(b));

+ resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

module bbb ((* b *) .e(e),.f(f));

-resistor #((* a *) .r(100)) r1 (.p(a),.n(b));

-resistor #(.r(200),(* d *) .$mfactor(2)) r2 (.p(a),.n(b));

-resistor #((* d *) .r(200),.$mfactor(2)) r2a (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200),.$mfactor(2)) r4 (.p(a),.n(b));

-resistor #(.r(100)) r5 (.p(a),.n(b));

-resistor #(.r(200),.$mfactor(2)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-aaa #() a2 (.c(b),.d(a));

-aaa #() a3 (.c(a),(* u *) .d(b));

-aaa #() a4 (.c(b),(* u *) .d(a));

+ resistor #((* a *) .r(100)) r1 (.p(a),.n(b));

+ resistor #(.r(200),(* d *) .$mfactor(2)) r2 (.p(a),.n(b));

+ resistor #((* d *) .r(200),.$mfactor(2)) r2a (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200),.$mfactor(2)) r4 (.p(a),.n(b));

+ resistor #(.r(100)) r5 (.p(a),.n(b));

+ resistor #(.r(200),.$mfactor(2)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ aaa #() a2 (.c(b),.d(a));

+ aaa #() a3 (.c(a),(* u *) .d(b));

+ aaa #() a4 (.c(b),(* u *) .d(a));

endmodule // bbb

""

diff --git a/tests/==out/u_attrib.3.gc.out b/tests/==out/u_attrib.3.gc.out
index f61f0218..95ac6f57 100644
--- a/tests/==out/u_attrib.3.gc.out
+++ b/tests/==out/u_attrib.3.gc.out

@@ -27,29 +27,29 @@

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

@@ -85,29 +85,29 @@ endmodule // bbb

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

diff --git a/tests/==out/u_attrib.4.gc.out b/tests/==out/u_attrib.4.gc.out
index 2ced385d..4b99a04e 100644
--- a/tests/==out/u_attrib.4.gc.out
+++ b/tests/==out/u_attrib.4.gc.out

@@ -27,29 +27,29 @@

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

@@ -85,29 +85,29 @@ endmodule // bbb

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

@@ -143,29 +143,29 @@ endmodule // bbb

" "

"list"

(* a *) module aaa (.c(c),.d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

(* h *) module bbb (.e(e),.f(f));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-(* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-(* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

-(* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),.d(b));

-(* e *) aaa #() a2 (.c(a),.d(b));

-a1 #() a3 (.c(a),.d(b));

-a2 #() a4 (.c(a),.d(b));

-(* f *) a1 #() a5 (.c(a),.d(b));

-(* g *) a2 #() a6 (.c(a),.d(b));

-(* i, j *) a1 #() a7 (.c(a),.d(b));

-(* k, l *) a2 #() a8 (.c(a),.d(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ (* b *) resistor #(.r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ (* c *) resistor #(.r(100)) r5 (.p(a),.n(b));

+ (* d *) resistor #(.r(200)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),.d(b));

+ (* e *) aaa #() a2 (.c(a),.d(b));

+ a1 #() a3 (.c(a),.d(b));

+ a2 #() a4 (.c(a),.d(b));

+ (* f *) a1 #() a5 (.c(a),.d(b));

+ (* g *) a2 #() a6 (.c(a),.d(b));

+ (* i, j *) a1 #() a7 (.c(a),.d(b));

+ (* k, l *) a2 #() a8 (.c(a),.d(b));

endmodule // bbb

""

diff --git a/tests/==out/u_attrib.5.gc.out b/tests/==out/u_attrib.5.gc.out
index 2edef075..85ed4596 100644
--- a/tests/==out/u_attrib.5.gc.out
+++ b/tests/==out/u_attrib.5.gc.out

@@ -25,27 +25,27 @@

" "

"list"

(* x, y,z *) module aaa ((* c, d=e *) .c(c),(* d *) .d(d));

-resistor #(.r(100)) r1 (.p(a),.n(b));

-resistor #((* r *) .r(200)) r2 (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200)) r4 (.p(a),.n(b));

-resistor #(.r(100)) r5 (.p(a),.n(b));

-resistor #(.r(200)) r6 (.p(a),.n(b));

+ resistor #(.r(100)) r1 (.p(a),.n(b));

+ resistor #((* r *) .r(200)) r2 (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200)) r4 (.p(a),.n(b));

+ resistor #(.r(100)) r5 (.p(a),.n(b));

+ resistor #(.r(200)) r6 (.p(a),.n(b));

endmodule // aaa

module bbb ((* b *) .e(e),.f(f));

-resistor #((* a, b *) .r(100)) r1 (.p(a),.n(b));

-resistor #(.r(200),(* d, e=f, g,h *) .$mfactor(2)) r2 (.p(a),.n(b));

-resistor #((* d *) .r(200),.$mfactor(2)) r2a (.p(a),.n(b));

-resistor #((* d *) .r(200),(* x *) .$mfactor(2)) r2b (.p(a),.n(b));

-resistor #(.r(100)) r3 (.p(a),.n(b));

-resistor #(.r(200),.$mfactor(2)) r4 (.p(a),.n(b));

-resistor #(.r(100)) r5 (.p(a),.n(b));

-resistor #(.r(200),.$mfactor(2)) r6 (.p(a),.n(b));

-aaa #() a1 (.c(a),(* c, d=e,f, g *) .d(b));

-aaa #() a2 (.c(b),(* a, b, c *) .d(a));

-aaa #() a3 (.c(a),(* u *) .d(b));

-aaa #() a4 (.c(b),(* u *) .d(a));

+ resistor #((* a, b *) .r(100)) r1 (.p(a),.n(b));

+ resistor #(.r(200),(* d, e=f, g,h *) .$mfactor(2)) r2 (.p(a),.n(b));

+ resistor #((* d *) .r(200),.$mfactor(2)) r2a (.p(a),.n(b));

+ resistor #((* d *) .r(200),(* x *) .$mfactor(2)) r2b (.p(a),.n(b));

+ resistor #(.r(100)) r3 (.p(a),.n(b));

+ resistor #(.r(200),.$mfactor(2)) r4 (.p(a),.n(b));

+ resistor #(.r(100)) r5 (.p(a),.n(b));

+ resistor #(.r(200),.$mfactor(2)) r6 (.p(a),.n(b));

+ aaa #() a1 (.c(a),(* c, d=e,f, g *) .d(b));

+ aaa #() a2 (.c(b),(* a, b, c *) .d(a));

+ aaa #() a3 (.c(a),(* u *) .d(b));

+ aaa #() a4 (.c(b),(* u *) .d(a));

endmodule // bbb

""

diff --git a/tests/==out/u_hsparam.0.gc.out b/tests/==out/u_hsparam.0.gc.out
index 197cce1d..fbfadab3 100644
--- a/tests/==out/u_hsparam.0.gc.out
+++ b/tests/==out/u_hsparam.0.gc.out

@@ -1,9 +1,9 @@

module a (.x(x),.y(y));

-resistor #(.r(1),.$mfactor(2)) r (.p(x),.n(y));

+ resistor #(.r(1),.$mfactor(2)) r (.p(x),.n(y));

endmodule // a

module b (.x(x),.y(y));

-a #(.$mfactor(.33333)) r (.x(x),.y(y));

+ a #(.$mfactor(.33333)) r (.x(x),.y(y));

endmodule // b

isource #(.dc(1)) i (.p(0円 ),.n(x));

diff --git a/tests/==out/u_hsparam.1.gc.out b/tests/==out/u_hsparam.1.gc.out
index 0e8516a3..54e29b94 100644
--- a/tests/==out/u_hsparam.1.gc.out
+++ b/tests/==out/u_hsparam.1.gc.out

@@ -1,13 +1,13 @@

module a (.x(x),.y(y));

-resistor #(.r(1),.$mfactor(2)) r (.p(x),.n(y));

+ resistor #(.r(1),.$mfactor(2)) r (.p(x),.n(y));

endmodule // a

module b (.x(x),.y(y));

-a #() r (.x(x),.y(y));

+ a #() r (.x(x),.y(y));

endmodule // b

module c (.x(x),.y(y));

-b #(.$mfactor(.33333)) r (.x(x),.y(y));

+ b #(.$mfactor(.33333)) r (.x(x),.y(y));

endmodule // c

isource #(.dc(1)) i (.p(0円 ),.n(x));

diff --git a/tests/==out/u_hsparam.2.gc.out b/tests/==out/u_hsparam.2.gc.out
index 8ad78d1c..924876ea 100644
--- a/tests/==out/u_hsparam.2.gc.out
+++ b/tests/==out/u_hsparam.2.gc.out

@@ -5,16 +5,16 @@

2. 0. 42.

3. 0. 63.

module a (.x(x),.y(y));

-isource #(.dc(1.),.$mfactor(7)) i (.p(x),.n(y));

+ isource #(.dc(1.),.$mfactor(7)) i (.p(x),.n(y));

endmodule // a

module b (.x(x),.y(y));

-//a r(x,y)

-a #(.$mfactor(1)) r (.x(x),.y(y));

+ //a r(x,y)

+ a #(.$mfactor(1)) r (.x(x),.y(y));

endmodule // b

module c (.x(x),.y(y));

-b #(.$mfactor(3)) r (.x(x),.y(y));

+ b #(.$mfactor(3)) r (.x(x),.y(y));

endmodule // c

ground gnd;

diff --git a/tests/==out/u_hsparam.3.gc.out b/tests/==out/u_hsparam.3.gc.out
index 5c20505e..26829139 100644
--- a/tests/==out/u_hsparam.3.gc.out
+++ b/tests/==out/u_hsparam.3.gc.out

@@ -1,5 +1,5 @@

module a (.x(x),.y(y));

-isource #((* dc *) .dc(1.),(* mf *) .$mfactor(7),(* foo *) .$foo(3)) i (.p(x),.n(y));

+ isource #((* dc *) .dc(1.),(* mf *) .$mfactor(7),(* foo *) .$foo(3)) i (.p(x),.n(y));

endmodule // a

Gnucap System status

diff --git a/tests/==out/u_hsparam.temp1.gc.out b/tests/==out/u_hsparam.temp1.gc.out
index 43e5d315..57c77953 100644
--- a/tests/==out/u_hsparam.temp1.gc.out
+++ b/tests/==out/u_hsparam.temp1.gc.out

@@ -1,9 +1,9 @@

module rr (.a(a),.b(b),.c(c),.d(d),.e(e),.ref(ref));

-resistor #(.r($temperature())) r (.p(a),.n(ref));

-resistor #(.r($temperature())) r (.p(b),.n(ref));

-resistor #(.r($vt())) r (.p(c),.n(ref));

-resistor #(.r($vt($temperature()))) r (.p(d),.n(ref));

-resistor #(.r($vt(200))) r (.p(e),.n(ref));

+ resistor #(.r($temperature())) r (.p(a),.n(ref));

+ resistor #(.r($temperature())) r (.p(b),.n(ref));

+ resistor #(.r($vt())) r (.p(c),.n(ref));

+ resistor #(.r($vt($temperature()))) r (.p(d),.n(ref));

+ resistor #(.r($vt(200))) r (.p(e),.n(ref));

endmodule // rr

ground gnd;

diff --git a/tests/==out/u_hsparam.temp1b.gc.out b/tests/==out/u_hsparam.temp1b.gc.out
index 643ceade..b7ffb9cf 100644
--- a/tests/==out/u_hsparam.temp1b.gc.out
+++ b/tests/==out/u_hsparam.temp1b.gc.out

@@ -1,7 +1,7 @@

module rr (.a(a),.b(b),.c(c),.ref(ref));

-resistor #(.r($temperature())) r (.p(a),.n(ref));

-resistor #(.r($temperature)) r (.p(b),.n(ref));

-resistor #(.r($vt())) r (.p(c),.n(ref));

+ resistor #(.r($temperature())) r (.p(a),.n(ref));

+ resistor #(.r($temperature)) r (.p(b),.n(ref));

+ resistor #(.r($vt())) r (.p(c),.n(ref));

endmodule // rr

ground gnd;

diff --git a/tests/d_subckt.bin.0.ckt b/tests/d_subckt.bin.0.ckt
new file mode 100644
index 00000000..93a8c5c6
--- /dev/null
+++ b/tests/d_subckt.bin.0.ckt

@@ -0,0 +1,15 @@

+* subckt, param, bin test

+.options trace

+

+.subckt foo (a k)

+.model mydio d is=1e-9

+.model mydio d is=1e-10

+d1 (a k) mydio area=1

+.ends

+

+i9 (0 9) 1

+x9 (9 0) foo

+

+.print op v(nodes)

+.op

+.end

diff --git a/tests/lang_verilog.dup.0.gc b/tests/lang_verilog.dup.0.gc
new file mode 100644
index 00000000..f87e81ee
--- /dev/null
+++ b/tests/lang_verilog.dup.0.gc

@@ -0,0 +1,17 @@

+verilog

+

+module aaa (a,b);

+ resistor #(100) r1(a,b);

+ r1 #() r2(a,b);

+ r2 #(.r(300)) r2(a,b);

+endmodule;

+

+list

+

+aaa a1(0円 , a);

+isource #(.dc(1)) i1(0円 , a);

+

+print dc v(a)

+dc

+

+end

diff --git a/tests/lang_verilog.dup.1.gc b/tests/lang_verilog.dup.1.gc
new file mode 100644
index 00000000..176f0ae9
--- /dev/null
+++ b/tests/lang_verilog.dup.1.gc

@@ -0,0 +1,21 @@

+verilog

+

+module aaa (a,b);

+ module bbb (a,b);

+ resistor #(1) r1(a,b);

+ endmodule;

+ module bbb (a,b);

+ resistor #(2) r1(a,b);

+ endmodule;

+ bbb #() r2(a,b);

+endmodule;

+

+list

+

+aaa a1(0円 , a);

+isource #(.dc(1)) i1(0円 , a);

+

+print dc v(a)

+dc

+

+end