| -rw-r--r-- | tests/lang_verilog.dup.0.gc | 17 |
diff --git a/tests/lang_verilog.dup.0.gc b/tests/lang_verilog.dup.0.gc new file mode 100644 index 00000000..f87e81ee --- /dev/null +++ b/tests/lang_verilog.dup.0.gc @@ -0,0 +1,17 @@ +verilog + +module aaa (a,b); + resistor #(100) r1(a,b); + r1 #() r2(a,b); + r2 #(.r(300)) r2(a,b); +endmodule; + +list + +aaa a1(0円 , a); +isource #(.dc(1)) i1(0円 , a); + +print dc v(a) +dc + +end |