Synopsys Platform Architect models provide commonly required architectural components including generic traffic generators, interconnects, memory subsystems, and embedded processors. This enables architects and system designers to efficiently design, analyze, and optimize the performance, power, and cost of SoC architectures in Platform Architect.
Generic:
SBL-TLM2-FT (AXI)
SBL-GCCI (ACE)
Arteris:
Arteris FlexNoC & Ncore
Arm:
Arm Performance Models
Arm AHB/APB
Synopsys:
Synopsys AXI
Generic:
Multiport memory controller (GMPMC)
SRAM controller
Cache controller
NoC
Synopsys:
uMCTL2, DDR5, LPDDR5, LPDDR6, and HBM3 Memory Controller
RTL Co-simulation
Die-to-Die
Task-based and Trace-based Workload Models
Cycle Accurate Processor:
ARC
Tensilica
RTL Co-simulation/emulation