Makefile dependency issue

Question

I'm trying to compile an example code where I added a new file under a new directory but I keep getting a dependency problem. I have added a file "ipc.c" under "/interface". I have added the source file to "srcs" and also added the directory with "-I/interface". The Makefile looks as follows:

#
# ======== Makefile ========
#
include ../products.mak
srcs = main_host.c interface/ipc.c
objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.o$(SUFFIX),$(srcs)))
libs = $(SYSLINK_INSTALL_DIR)/packages/ti/syslink/lib/syslink.a_$(PROFILE)
MAKEVARS = \
SYSLINK_INSTALL_DIR=$(SYSLINK_INSTALL_DIR) \
PKGPATH=$(PKGPATH)
all:
@$(ECHO) "!"
@$(ECHO) "! Making $@ ..."
$(MAKE) $(MAKEVARS) PROFILE=debug SUFFIX=v5T togs2_host
$(MAKE) $(MAKEVARS) PROFILE=release SUFFIX=v5T togs2_host
install:
@$(ECHO) "#"
@$(ECHO) "# Making $@ ..."
@$(MKDIR) $(INSTALL_DIR)/debug
$(CP) bin/debug/togs2_host $(INSTALL_DIR)/debug
@$(MKDIR) $(INSTALL_DIR)/release
$(CP) bin/release/togs2_host $(INSTALL_DIR)/release
clean::
$(RMDIR) bin
# 
# 
# ======== rules ========
#
togs2_host: bin/$(PROFILE)/togs2_host
bin/$(PROFILE)/togs2_host: $(objs) $(libs)
@$(ECHO) "##"
@$(ECHO) "## Making $@ ..."
$(LD) $(LDFLAGS) -o $@ $^ $(LDLIBS)
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.h
bin/$(PROFILE)/obj/%.o$(SUFFIX): %.c
@$(ECHO) "###"
@$(ECHO) "### Making $@ ..."
$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $<
# ======== create output directories ========
ifneq (clean,$(MAKECMDGOALS))
ifneq (,$(PROFILE))
ifeq (,$(wildcard bin/$(PROFILE)))
$(shell $(MKDIR) -p bin/$(PROFILE))
endif
ifeq (,$(wildcard bin/$(PROFILE)/obj))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj)
endif
endif
endif
# ======== install validation ========
ifeq (install,$(MAKECMDGOALS))
ifeq (,$(INSTALL_DIR))
$(error must specify INSTALL_DIR)
endif
endif
# ======== toolchain macros ========
ifeq (v5T,$(SUFFIX))
CC = $(CS_ARM_INSTALL_DIR)gcc -c -MD -MF [email protected] -march=armv5t
AR = $(CS_ARM_INSTALL_DIR)ar cr
LD = $(CS_ARM_INSTALL_DIR)gcc
CPPFLAGS = -D_REENTRANT -Dxdc_target_name__=GCArmv5T \
-Dxdc_target_types__=gnu/targets/arm/std.h
CFLAGS = -Wall -ffloat-store -fPIC -Wunused -Dfar= $(CCPROFILE_$(PROFILE)) \
-I. -I/interface $(addprefix -I,$(subst +, ,$(PKGPATH))) 
LDFLAGS = $(LDPROFILE_$(PROFILE)) -Wall -Wl,[email protected]
LDLIBS = -lpthread -lc
CCPROFILE_debug = -ggdb -D DEBUG
CCPROFILE_release = -O3 -D NDEBUG
LDPROFILE_debug = -ggdb
LDPROFILE_release = -O3
endif

I keep getting this error: fatal error: opening dependency file bin/debug/obj/interface/ipc.ov5T.dep: No such file or directory

This is how the the products.mak looks like:

#
# ======== products.mak ========
#
DEPOT = /opt
BIOS_INSTALL_DIR = $(DEPOT)/bios_6_33_01_25
IPC_INSTALL_DIR = $(DEPOT)/ti/ipc_1_23_05_40
SYSLINK_INSTALL_DIR = $(DEPOT)/syslink_2_10_02_17
TI_C6X_INSTALL_DIR = $(DEPOT)/ti/ccsv5/tools/compiler/c6000
CS_ARM_INSTALL_DIR = $(DEPOT)/CodeSourcery/Sourcery_G++_Lite/bin/arm-none-linux-gnueabi-
XDC_INSTALL_DIR = $(DEPOT)/xdctools_3_23_00_32
PKGPATH := $(SYSLINK_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(BIOS_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
PKGPATH := $(PKGPATH)+$
# Use this goal to print your product variables.
.show-products:
 @echo "BIOS_INSTALL_DIR = $(BIOS_INSTALL_DIR)"
 @echo "IPC_INSTALL_DIR = $(IPC_INSTALL_DIR)"
 @echo "SYSLINK_INSTALL_DIR = $(SYSLINK_INSTALL_DIR)"
 @echo "TI_ARM_INSTALL_DIR = $(TI_ARM_INSTALL_DIR)"
 @echo "TI_C6X_INSTALL_DIR = $(TI_C6X_INSTALL_DIR)"
 @echo "CS_ARM_INSTALL_DIR = $(CS_ARM_INSTALL_DIR)"
 @echo "XDC_INSTALL_DIR = $(XDC_INSTALL_DIR)"
# ======== standard macros ========
ifneq (,$(wildcard $(XDC_INSTALL_DIR)/bin/echo.exe))
 # use these on Windows
 CP = $(XDC_INSTALL_DIR)/bin/cp
 ECHO = $(XDC_INSTALL_DIR)/bin/echo
 MKDIR = $(XDC_INSTALL_DIR)/bin/mkdir -p
 RM = $(XDC_INSTALL_DIR)/bin/rm -f
 RMDIR = $(XDC_INSTALL_DIR)/bin/rm -rf
else
 # use these on Linux
 CP = cp
 ECHO = echo
 MKDIR = mkdir -p
 RM = rm -f
 RMDIR = rm -rf
endif

I'm not understanding the Makefile completely as it's a code example I'm simply expanding.

• eriktous: You're not showing us the whole problem. At the top, this makefile includes the file ../products.mak. There's likely a line in that file that includes a .dep file for each object file, but it's not looking in the right directory for the file you added (or you could say that you added the file in the wrong directory ;) ).
• bPratik: StackO Aberdeen Meetup 2012: See SO Meetup Link for more info. Seeing you are based in Aberdeen, please try to attend. I'll remove this comment tomorrow. Apologies, but there is no other way to contact on SO.

Answer 1

For the record: The error "fatal error: opening dependency file [...]: No such file or directory" can also be caused by a too long path. Happened to me on Cygwin/Windows with a path that was way over 200 characters (didn't check exactly).

Answer 2

Got it working.

Needed to add a rule to create the output directories. So I added

ifeq (,$(wildcard bin/$(PROFILE)/obj/interface))
$(shell $(MKDIR) -p bin/$(PROFILE)/obj/interface)
endif

Answer 3

This makefile is pretty convoluted, so a certain amount of guesswork is required, but I think the trouble is that it doesn't know how to find interface/ipc.c. Try adding this line at the bottom and see if helps:

vpath %.c interface

If it doesn't, we can try some other things. (And if it does, I can suggest some ways to simplify the makefile.)

• Onklen: Still doesn't work with that line added at the bottom of the Makefile.
• Beta: @Onklen, this is strange. There's nothing in what you've shown us that involves .dep files at all. I'd like to try simplifying the problem, posting some reduced makefiles for you to try; which OS are you using?
• Onklen: I'm using Ubuntu 11.10. I'm cross compiling for an OMAPL138 chip.