MakeFiles and dependencies

Question

I'm writing a makefile and I can't figure out how to include all my source files without having to write all source file I want to use. Here is the makefile I'm currently using:

GCC = $(GNUARM_HOME)\bin\arm-elf-gcc.exe
SOURCES=ShapeApp.cpp Square.cpp Circle.cpp Shape.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS) 
#$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.cpp.o:
 $(GCC) -c $< -o $@

How do I automatically add new source file without having to add it to the sources line?

• Jonathan Leffler: Outside of toy projects, you do not want to do this very often. You get into trouble the first time you make a backup copy of a file, or leave a bit of test code lying around. Not listing exactly the modules that make up the program is a recipe for trouble. If each file was a complete self-contained program, which is what Dirk suggested, it is more sensible.

Answer 1

Here is something I have used in an examples/ directory where each file is mapped one-to-one to an executable:

sources := $(wildcard *.cpp)
programs := $(sources:.cpp=)
[ more settings about compiler flags, linker options, ...]
all : $(programs)

That can be enough as make knows how to turn a .cpp file into an object file and then into an executable. Note that this is on Linux so for Windoze you'd probably need to do

programs := $(sources:.cpp=.exe)

to append the .exe.

• rjh: The OP only wants one executable. (Although he can probably figure out the rest from your answer)
• Dirk is no longer here: Correct. All he needs is the sources statement.