Make Implicit Dependancy

Question

In a Makefile, is there any way of making a rule an implicit dependency of all other rules?

Say, for instance, i wanted a rule run whenever the Makefile is run, regardless of which rule is actually being requested. How would i do that?

Answer 1

I have no idea why you'd want to do this, but in GNU make you can do this by -include-ing a .PHONY file:

.PHONY: run-always
-include run-always
run-always:
 echo "trololol"

• Beta: +1. I hate Jack Kelly with every fiber of my being, but this is ingenious.
• Woodrow Douglass: Brilliant...thanks! The only reason i want to do this is to print some instructional text whenever the makefile is run.
• Jack Kelly: @Beta: The feeling's mutual, in that friendly-rivalry sort of way.
• Beta: Friendly riv... that's the kind of nemesis you think I am? Oh, it's on. I'm going to go kill one of my henchmen, maybe take a little "me time", then it's on.
• Matt Joiner: I don't see why you wouldn't want to do something, but bravo for having the solution.

Answer 2

Include a wildcard rule:

%: mydependency

I've tried this, the following makefile is a proof of concept

all: a b
a:
 touch $@
%: ccc
 #
ccc::
 touch ccc

Note the use of

1. Double-Colon Rule
2. Match-Anything Pattern Rule

In order to prevent the dependency from building unconditionally each time, you might want to make it an indirect dependency (requirement for the ccc:: rule above, instead of directly on the wildcard rule).

Good luck

• Woodrow Douglass: not exactly what i wanted. I'm thinking whether i run "make a" "make b" or "make", 'echo implicit dependency' will run. ` all: a b a: touch $@ b: touch $@ %: echo implicit dependancy ` edit: can't seem to get the code mini-markdown to work.
• sehe: @Woodrow: right I cannot parse that comment. Feel free to update your question and leave me a note