makefile with multiple dependencies for a single file

Question

I have a makefile similar to the following:

SRCS = a.c b.cpp
OBJS = objs/a.o objs/b.o
all: $(OBJS)
objs/%.o: %.c
 gcc -c $< -o $@
objs/%.o: %.cpp
 gcc -c $< -o $@

It seems to work. But I don't really understand why. Why doesn't it try to generate a.cpp and b.c?

as I read it : a.cpp is a prerequisite for objs/a.o and it should try to generate it. And because it doesn't find a matching rule for it - it should fail

Where am I wrong?

P.S - I execute my makefile using -r -R to avoid builtin rules

Answer 1

Make does not combine the prerequisite lists of different pattern rules.

When Make is looking for a way to build objs/a.o, it finds that the first pattern rule matches the target, and the prerequisite (a.c) exists. The second pattern rule matches the target, but the prerequisite (a.cpp) does not exist and cannot be built, so Make uses the first rule. Likewise, Make chooses the second rule over the first when looking for a way to build objs/b.o.

• user972014: Can you direct me to where it is mentioned? I looked for it in the GNU make and couldn't find it
• Beta: @user972014: The manual has sections on pattern rules and how they match. I don't know of a reference that states explicitly that the prerequisite lists are not combined, but it is implied in those sections.
• user972014: Here. I found it: "A pattern rule can be used to build a given file only if there is a target pattern that matches the file name, and all prerequisites in that rule either exist or can be built"

Answer 2

Make would try to generate a.cpp and b.c if these files depended on something else. However it is not the case here, these two files are leaves in the dependency tree, so Make has no reason to try to generate them.