SPEAR – Single Neuron Hardware Accelerator Engine. A collaborative hardware project combining full custom ASIC design and FPGA-based validation. The CHIP team designed a perceptron accelerator from RTL to GDSII using Synopsys tools and TSMC 28nm. The FPGA team built a working test platform on DE10-Lite. Developed with mentorship and technical suppo
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
Complete design of RISC-V SoC from basic RTL to GDSII
This repository documents my journey in the RISC-V Reference SoC Tapeout Program. The first 10 weeks focus on RTL design, synthesis, simulation, and verification using open-source tools like Yosys, Icarus Verilog, GTKWave, and OpenLane, building a foundation for full-chip tapeout.
Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)
An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full ×ばつ8 demux for 8-bit data — all the way from Verilog to GDSII.
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