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chisel

chipsalliance / chisel

Star 4.4k

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Oct 24, 2025
Scala

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab...

android ios ui uitableview uicollectionview xcode view css3 layout cocoapods xib storyboard constraints rtl grid-layout autolayout uiscrollview flexbox-layout layoutsubviews sizeclasses

Updated Apr 16, 2024
Objective-C

chipsalliance / rocket-chip

Star 3.6k

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Updated Sep 2, 2025
Scala

verilator

verilator / verilator

Star 3.1k

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Oct 24, 2025
C++

layoutBox / PinLayout

Star 2.4k

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

swift language swift-library ios cocoapod layout carthage layout-engine rtl swift-framework swift-3 ios-swift anchor ios-ui ios-lib margin chainable-methods uiview-extension left-language

Updated Jul 23, 2025
Swift

The-OpenROAD-Project / OpenROAD

Star 2.2k

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Oct 24, 2025
Verilog

ucb-bar / chipyard

Star 2k

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Oct 9, 2025
Scala

riscv-boom / riscv-boom

Star 2k

SonicBOOM: The Berkeley Out-of-Order Machine

scala berkeley boom rocket-chip chisel riscv rtl riscv-boom

Updated May 6, 2025
Scala

SpinalHDL / SpinalHDL

Star 1.9k

Scala based HDL

scala fpga vhdl rtl verilog

Updated Oct 13, 2025
Scala

MohammadYounes / rtlcss

Star 1.7k

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

css i18n postcss css3 mirror ltr rtl cascading-style-sheets postcss-plugin flip rtlcss right-to-left left-to-right

Updated Feb 18, 2025
JavaScript

The-OpenROAD-Project / OpenLane

Star 1.6k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 15, 2025
Python

pulp-platform / axi

Star 1.4k

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Oct 16, 2025
SystemVerilog

chili-chips-ba / wireguard-fpga

Star 1.2k

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

embedded fpga iss vpn rtl verilog risc-v wireguard verilator cocotb vproc

Updated Oct 23, 2025
Verilog

siliconcompiler / siliconcompiler

Star 1.1k

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Oct 24, 2025
Python

kartik-v / bootstrap-star-rating

Star 1.1k

A simple yet powerful JQuery star rating plugin with fractional rating support.

javascript css jquery rating css-styles rtl caption star bootstrap-star-rating rate-control change-stars star-symbols fractional

Updated Mar 22, 2023
JavaScript

syntacore / scr1

Star 937

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Nov 15, 2024
SystemVerilog

chipsalliance / Cores-VeeR-EH1

Star 901

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

ultraembedded / cores

Sponsor

Star 840

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

eldraco / Salamandra

Star 837

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

python threshold microphone sound rtl sdr microphones spy spy-microphones salamandra find-microphones detect-microphones

Updated Jan 11, 2021
Python

WangXuan95 / FPGA-USB-Device

Star 826

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器,可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备,只需要3个FPGA普通IO,而不需要额外的接口芯片。

keyboard fpga usb rtl verilog cdc uvc usb-controller usb-hid usb-audio usb-uart usb-cdc usb-serial usb-keyboard usb-device usb-camera usb-microphone usb-uvc usb-speaker usb-disk

Updated Dec 6, 2024
Verilog

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