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All 15 Verilog 7 C++ 2 SystemVerilog 2 TL-Verilog 1

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mnurczynski / pi

Star 14

My very own CPU architecture! Emulator availible!

cpp digital hardware assembly architecture emulation assembly-language computer-architecture microcode emulators instruction-set-architecture digital-design cpp-programming hardware-design emulator-development digital-design-and-computer-organization

Updated Jun 11, 2025
C++

Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGA

Star 7

Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).

fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor

Updated Jul 21, 2025
SystemVerilog

f3rhd / risccore

Star 6

5-Stage Pipelined RISC-V CPU + FS Language

programming-language cpu compiler-design riscv-asm riscv32i digital-design-and-computer-organization

Updated Oct 19, 2025
C++

ArvinDelavari / Digital-Circuits-Verilog

Star 5

Sample Verilog codes for digital circuits

cpu vscode verilog computer-architecture hdl risc-v iverilog digital-design hardware-description-language cpu-design digital-design-and-computer-organization

Updated Oct 22, 2023
Verilog

DopeBiscuit / IEEE-Digital-IC-Design

Star 4

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

logic-design verilog-project digital-design-and-computer-organization

Updated Oct 10, 2023
Verilog

SpencerDeMera / 8-Bit-ALU-Circuit

Star 2

This project is my design of a basic ALU that can perform addition, subtraction, and bitwise logic operations. This project was designed in Logisim Evolution and implemented with TTL logic chips on breadboards.

digital-design logic-design digital-design-and-computer-organization

Updated Jun 27, 2023

Prajna-Ramamurthy / Pseudo-Random-Binary-Sequence-Generator

Star 1

Digital Design and Computer Organisation Mini-project

arm fpga project verilog college-project digital-design computer-organization prbs-generator mini-project sequence-generation pseudo-random-generator field-programmable-gate-arrays verilog-project sequence-generator prbs ddco arm7tdmi digital-design-and-computer-organization binary-sequence-generator

Updated Aug 7, 2023
Verilog

VishalS-HK / DDCO-Lab-UE21CS251A

Star 1

A Repo that contains the source code for Digital Design and Computer Organisation course.

verilog icarus-verilog digital-design-and-computer-organization

Updated Jan 4, 2023
Verilog

OccupyMars2025 / Digital-Design-with-an-introduction-to-the-Verilog-HDL

Star 0

by M. Morris Mano, Michael D. Ciletti. 5th Edition

digital-design-and-computer-organization

Updated Apr 6, 2023

rao-shreyashree / ddco-verilog

Star 0

Collection of foundational digital logic modules implemented in Verilog, including gates, adders, multiplexers, demultiplexers, encoders, and decoders. Simulated using Icarus Verilog and visualized with GTKWave for waveform analysis.

hardware-designs computer-architecture verilog-hdl digital-design-and-computer-organization