38029: 02/01/01: satya: Virtex-II FPGA Chips Availability
38031: 02/01/01: Colin Cook: Re: Virtex-II FPGA Chips Availability
38032: 02/01/02: Orlls: Verilog code
38042: 02/01/02: Brad Eckert: Re: Verilog code
38033: 02/01/02: divya: FPGA
38039: 02/01/02: Andy Peters: Re: FPGA
38034: 02/01/02: divya: FLOORPLANNING IN XILINX
38118: 02/01/06: Kevin Brace: Re: FLOORPLANNING IN XILINX
38035: 02/01/02: renjini: floorplanning
38119: 02/01/06: Kevin Brace: Re: floorplanning
38036: 02/01/02: Matthias Weber: asic vs. fpga
38044: 02/01/02: Rene Tschaggelar: Re: asic vs. fpga
38064: 02/01/03: Noel Klonsky: Re: asic vs. fpga
38072: 02/01/04: Peter Alfke: Re: asic vs. fpga
38077: 02/01/04: Thomas Stanka: Re: asic vs. fpga
38095: 02/01/04: Richard Iachetta: Re: asic vs. fpga
38099: 02/01/04: S. Ramirez: Re: asic vs. fpga
38100: 02/01/04: Peter Alfke: Re: asic vs. fpga
38104: 02/01/05: <hamish@cloud.net.au>: Re: asic vs. fpga
38108: 02/01/05: Rick Filipkiewicz: Re: asic vs. fpga
38124: 02/01/06: Kim Enkovaara: Re: asic vs. fpga
38266: 02/01/10: Martin Darwin: Re: asic vs. fpga
38276: 02/01/10: Rick Filipkiewicz: Re: asic vs. fpga
38302: 02/01/11: Thomas Stanka: Re: asic vs. fpga
38304: 02/01/11: Ray Andraka: Re: asic vs. fpga
38310: 02/01/11: Martin Darwin: Re: asic vs. fpga
38336: 02/01/11: jay mitchell: Re: asic vs. fpga
38362: 02/01/12: Petter Gustad: Re: asic vs. fpga
42188: 02/04/18: Sujatha Sriram: fpga limitation
42191: 02/04/18: Russell: Re: fpga limitation
42230: 02/04/18: Manfred Kraus: Re: fpga limitation
42236: 02/04/18: Jay: Re: fpga limitation
42240: 02/04/18: Austin Lesea: Re: fpga limitation
42251: 02/04/18: Tim: Re: fpga limitation
42254: 02/04/18: John_H: Re: fpga limitation
42257: 02/04/18: Austin Lesea: Re: fpga limitation
42321: 02/04/20: Hal Murray: Re: fpga limitation
42377: 02/04/22: Austin Lesea: Re: fpga limitation
42644: 02/04/30: Hal Murray: Re: fpga limitation
42648: 02/04/30: Tim: Re: fpga limitation
43042: 02/05/10: Rick Filipkiewicz: Re: fpga limitation
42386: 02/04/22: John_H: Re: fpga limitation
42295: 02/04/19: Jay: Re: fpga limitation
42310: 02/04/20: Tim: Re: fpga limitation
42268: 02/04/19: Marco Serafini: Re: fpga limitation
38045: 02/01/02: Jason Berringer: A Fast counter in VHDL?
38047: 02/01/03: S. Ramirez: Re: A Fast counter in VHDL?
38067: 02/01/03: Jason Berringer: Re: A Fast counter in VHDL?
38070: 02/01/04: Peter Alfke: Re: A Fast counter in VHDL?
38083: 02/01/04: Falk Brunner: Re: A Fast counter in VHDL?
38113: 02/01/06: Ray Andraka: Re: A Fast counter in VHDL?
38132: 02/01/06: Jason Berringer: Re: A Fast counter in VHDL?
38048: 02/01/03: Andreas Schweizer: Re: A Fast counter in VHDL?
38085: 02/01/04: Brad Eckert: Re: A Fast counter in VHDL?
38046: 02/01/03: Kenneth: Problem/Question about the timing report on Xilinx ISE 4.1
38056: 02/01/03: <hamish@cloud.net.au>: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38075: 02/01/04: Kenneth: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38079: 02/01/04: <hamish@cloud.net.au>: Re: Problem/Question about the timing report on Xilinx ISE 4.1
38049: 02/01/03: Alex Sherstuk: Q: Cable for multiple LVDS signals - ?
38058: 02/01/03: Austin Lesea: Re: Q: Cable for multiple LVDS signals - ?
38059: 02/01/03: Patrick McGuirk: Re: Cable for multiple LVDS signals - ?
38060: 02/01/03: Petter Gustad: Re: Q: Cable for multiple LVDS signals - ?
38050: 02/01/02: Antonio: Large ROM question
38052: 02/01/03: Daniel Yap: Help on RAM-based Shift Registers
38053: 02/01/03: Peter van Beek: PCI Solution: LogiCore?
38065: 02/01/03: clevin1234: Re: PCI Solution: LogiCore?
38066: 02/01/03: Colin Cook: Re: PCI Solution: LogiCore?
38068: 02/01/03: Austin Franklin: Re: PCI Solution: LogiCore?
38078: 02/01/04: Peter van Beek: Re: PCI Solution: LogiCore?
38084: 02/01/04: Austin Franklin: Re: PCI Solution: LogiCore?
38148: 02/01/07: John Jakson: Re: PCI Solution: LogiCore?
38548: 02/01/17: Stefan Klein: Re: PCI Solution: LogiCore?
38554: 02/01/17: Iwo Mergler: Re: PCI Solution: LogiCore?
39091: 02/01/31: Peter van Beek: Re: PCI Solution: LogiCore?
38076: 02/01/04: Kevin Brace: Re: PCI Solution: LogiCore?
38097: 02/01/04: Eric Smith: Re: PCI Solution: LogiCore?
38054: 02/01/03: Ashley: Automatically pipeline combinatorial EDIF
38055: 02/01/03: Steven Derrien: Re: Automatically pipeline combinatorial EDIF
38057: 02/01/03: Andreas Wassatsch: Re: Automatically pipeline combinatorial EDIF
38069: 02/01/03: Doug: Spartan-IIE interfacing issues
38080: 02/01/04: Kevin Brace: Re: Spartan-IIE interfacing issues
38081: 02/01/04: Rick Filipkiewicz: Re: Spartan-IIE interfacing issues
38088: 02/01/04: Austin Lesea: Re: Spartan-IIE interfacing issues
38298: 02/01/11: rickman: Re: Spartan-IIE interfacing issues
38316: 02/01/11: Austin Lesea: Re: Spartan-IIE interfacing issues
38073: 02/01/03: Markus Meng: ACTEL SX-A serie and ROM implementation ...
38082: 02/01/04: Falk Brunner: Re: ACTEL SX-A serie and ROM implementation ...
38074: 02/01/03: Antonio: conv_integer problem ???
39385: 02/02/07: Madhu: Re: conv_integer problem ???
38086: 02/01/04: Chuck Woodring: multiplexing a clock
38090: 02/01/04: Falk Brunner: Re: multiplexing a clock
38092: 02/01/04: Steve Rencontre: Re: multiplexing a clock
38093: 02/01/04: Bob Perlman: Re: multiplexing a clock
38087: 02/01/04: Claus Ritter: Configuration Times of FPGAs
38089: 02/01/04: Falk Brunner: Re: Configuration Times of FPGAs
38091: 02/01/04: Ulf Samuelsson: Re: Configuration Times of FPGAs
38096: 02/01/04: Chris Stinson: Re: Configuration Times of FPGAs
38094: 02/01/04: dev: help with older xilinx fpga's
38098: 02/01/04: Peter Alfke: Re: help with older xilinx fpga's
38101: 02/01/04: Yu Jun: ASIC faster than VirtexII FPGA?
38102: 02/01/05: Nicholas Weaver: Re: ASIC faster than VirtexII FPGA?
38106: 02/01/05: Muzaffer Kal: Re: ASIC faster than VirtexII FPGA?
38103: 02/01/04: Peter Alfke: Re: ASIC faster than VirtexII FPGA?
38105: 02/01/05: Muzaffer Kal: Re: ASIC faster than VirtexII FPGA?
38291: 02/01/10: Jay: Re: ASIC faster than VirtexII FPGA?
38314: 02/01/11: Austin Lesea: Re: ASIC faster than VirtexII FPGA?
38107: 02/01/05: jacky Renaux: RNS
38112: 02/01/06: Ray Andraka: Re: RNS
38109: 02/01/05: Matthias Weber: full custom design
38110: 02/01/05: Phil Hays: Re: full custom design
38111: 02/01/05: Muzaffer Kal: Re: full custom design
38114: 02/01/05: ssy: Q:where can I find an indepth manual about P&R in Quartus II ?
38116: 02/01/06: Kevin Brace: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
38122: 02/01/06: ssy: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
38115: 02/01/05: Orlls: simprims_ver/xilinxcorelib_ver /unisims_ver
38133: 02/01/06: Mike Treseler: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38137: 02/01/06: Orlls: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38141: 02/01/07: Utku Ozcan: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38154: 02/01/07: Brian Philofsky: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38682: 02/01/21: Paulo Dutra: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38117: 02/01/05: Nachiket Kapre: how do i program a Spartan FPGA
38123: 02/01/06: Falk Brunner: Re: how do i program a Spartan FPGA
38211: 02/01/08: swan: Re: how do i program a Spartan FPGA
38236: 02/01/09: Falk Brunner: Re: how do i program a Spartan FPGA
38125: 02/01/06: S. Ramirez: Re: how do i program a Spartan FPGA
38273: 02/01/10: Jon Elson: Re: how do i program a Spartan FPGA
38120: 02/01/05: Stout: Suitability of Atmel for project?
38121: 02/01/06: Jim Granville: Re: Suitability of Atmel for project?
38130: 02/01/06: Stout: Re: Suitability of Atmel for project?
38131: 02/01/07: Jim Granville: Re: Suitability of Atmel for project?
38155: 02/01/07: Stout: Re: Suitability of Atmel for project?
38162: 02/01/08: Jim Granville: Re: Suitability of Atmel for project?
38349: 02/01/11: Stout: Re: Suitability of Atmel for project?
38182: 02/01/08: Ulf Samuelsson: Re: Suitability of Atmel for project?
38187: 02/01/08: Falk Brunner: Re: Suitability of Atmel for project?
38166: 02/01/08: Marc: Re: Suitability of Atmel for project?
38126: 02/01/06: Ashok Mahadevan: Re: Suitability of Atmel for project?
38129: 02/01/06: Stout: Re: Suitability of Atmel for project?
38146: 02/01/07: Ulf Samuelsson: Re: Suitability of Atmel for project?
38127: 02/01/07: Daniel Yap: scalling ammulator problem
38128: 02/01/06: Nahum Abramovitch: 4 fpga configuration using 1 EPROM
38134: 02/01/06: Peter Alfke: Re: 4 fpga configuration using 1 EPROM
38135: 02/01/07: Przemyslaw Wegrzyn: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38138: 02/01/07: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38147: 02/01/07: Przemyslaw Wegrzyn: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38274: 02/01/10: Jon Elson: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38275: 02/01/10: rickman: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38277: 02/01/10: Rick Filipkiewicz: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38287: 02/01/10: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38286: 02/01/10: Peter Alfke: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38136: 02/01/06: <johnt246@yahoo.com>: Celoxica DK1 and Handel C
38139: 02/01/06: llossak: WARNING
38143: 02/01/07: Utku Ozcan: Re: WARNING
38157: 02/01/07: Andy Peters: Re: WARNING
38160: 02/01/07: Brian Philofsky: Re: WARNING
38173: 02/01/07: llossak: Re: WARNING
38184: 02/01/08: Brian Philofsky: Re: WARNING
38140: 02/01/06: cortyus: WARNING
38142: 02/01/07: Utku Ozcan: Re: WARNING
38144: 02/01/06: ssy: Re: WARNING
38150: 02/01/07: newman: Re: WARNING
38145: 02/01/07: Antonio: Synplify and Xilinx clock discovery
38156: 02/01/07: Brian Philofsky: Re: Synplify and Xilinx clock discovery
38149: 02/01/07: satya: Regarding frequency achieving in fpga design
38158: 02/01/07: Falk Brunner: Re: Regarding frequency achieving in fpga design
38159: 02/01/07: Brian Philofsky: Re: Regarding frequency achieving in fpga design
38164: 02/01/08: Rick Filipkiewicz: Re: Regarding frequency achieving in fpga design
38151: 02/01/07: Michael Boehnel: Article FPGA + Reliable Systems
38152: 02/01/07: Austin Lesea: Re: Article FPGA + Reliable Systems
38165: 02/01/07: ikauranen: Re: Article FPGA + Reliable Systems
38153: 02/01/07: <dainis@safequipment.com>: PDH MUX (E2,E3) VHLD cores
38431: 02/01/14: Juan-Luis Lopez: RE: PDH MUX (E2,E3) VHLD cores
38161: 02/01/07: Kevin Neilson: FIR Linear Interpolation
38175: 02/01/08: Jonathan Bromley: Re: FIR Linear Interpolation
38163: 02/01/07: ac-ic: I2C/SPI implementation on FPGA
38167: 02/01/07: newman: Re: I2C/SPI implementation on FPGA
38168: 02/01/07: Yu Jun: 128 bit compare delay kill me!
38169: 02/01/07: Eric Smith: Re: 128 bit compare delay kill me!
38172: 02/01/08: Nicholas Weaver: Re: 128 bit compare delay kill me!
38194: 02/01/08: Ray Andraka: Re: 128 bit compare delay kill me!
38171: 02/01/08: Nicholas Weaver: Re: 128 bit compare delay kill me!
38174: 02/01/08: Aki M Suihkonen: Re: 128 bit compare delay kill me!
38186: 02/01/08: John_H: Re: 128 bit compare delay kill me!
38170: 02/01/07: dotty1319: please tell me how to solve xilinx error xml
38237: 02/01/09: Dennis McCrohan: Re: please tell me how to solve xilinx error xml
38240: 02/01/09: Rick Filipkiewicz: Re: please tell me how to solve xilinx error xml
38176: 02/01/08: Kenily: multiply (*) 11000000000
38177: 02/01/08: Nicolas Matringe: Re: multiply (*) 11000000000
38180: 02/01/08: Keith R. Williams: Re: multiply (*) 11000000000
38280: 02/01/10: Jay: Re: multiply (*) 11000000000
38300: 02/01/11: Ray Andraka: Re: multiply (*) 11000000000
38303: 02/01/11: Allan Herriman: Re: multiply (*) 11000000000
38345: 02/01/11: Ken McElvain: Re: multiply (*) 11000000000
38354: 02/01/12: Ray Andraka: Re: multiply (*) 11000000000
38178: 02/01/08: Matthias Weber: latch vs. register
38185: 02/01/08: Peter Alfke: Re: latch vs. register
38192: 02/01/08: Eric Smith: Re: latch vs. register
38196: 02/01/08: John_H: Re: latch vs. register
38204: 02/01/08: Peter Alfke: Re: latch vs. register
38206: 02/01/09: Rick Filipkiewicz: Re: latch vs. register
38209: 02/01/08: Peter Alfke: Re: latch vs. register
38215: 02/01/09: Jonathan Bromley: Re: latch vs. register
38337: 02/01/11: Martin Rice: Re: latch vs. register
38342: 02/01/11: Peter Alfke: Re: latch vs. register
38179: 02/01/08: Matthias Weber: Xilinx XC2000, XC3000, XC4000 families
38181: 02/01/08: Keith R. Williams: Re: Xilinx XC2000, XC3000, XC4000 families
38183: 02/01/08: Ian Dedic: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
38189: 02/01/08: Austin Lesea: Re: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
38188: 02/01/08: David G.: S-video -> VGA
38193: 02/01/08: Eric Smith: Re: S-video -> VGA
38210: 02/01/09: David G.: Re: S-video -> VGA
38190: 02/01/08: Brad Eckert: ROM synthesis question
38195: 02/01/08: Dr. Jeff Jackson: Re: ROM synthesis question
38201: 02/01/08: Falk Brunner: Re: ROM synthesis question
38203: 02/01/08: Ray Andraka: Re: ROM synthesis question
38214: 02/01/09: Antonio: Re: ROM synthesis question
38254: 02/01/10: Ray Andraka: Re: ROM synthesis question
38191: 02/01/08: Kevin Brace: Repost: Should clock skew be included for setup time analysis?
38199: 02/01/08: Bob Perlman: Re: Repost: Should clock skew be included for setup time analysis?
38205: 02/01/08: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38230: 02/01/09: Kevin Brace: Re: Repost: Should clock skew be included for setup time analysis?
38252: 02/01/10: Bob Perlman: Re: Repost: Should clock skew be included for setup time analysis?
38253: 02/01/10: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38200: 02/01/08: Falk Brunner: Re: Repost: Should clock skew be included for setup time analysis?
38202: 02/01/08: Mike Treseler: Re: Repost: Should clock skew be included for setup time analysis?
38208: 02/01/09: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38207: 02/01/08: Marc Klingelhofer: Re: Repost: Should clock skew be included for setup time analysis?
38365: 02/01/12: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38369: 02/01/12: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38376: 02/01/13: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38440: 02/01/14: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38441: 02/01/14: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38465: 02/01/15: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38490: 02/01/15: Magnus Homann: Re: Repost: Should clock skew be included for setup time analysis?
38516: 02/01/16: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38371: 02/01/12: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38377: 02/01/13: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38389: 02/01/13: Rick Filipkiewicz: Re: Repost: Should clock skew be included for setup time analysis?
38394: 02/01/13: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38466: 02/01/15: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38475: 02/01/15: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38488: 02/01/15: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38514: 02/01/16: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38517: 02/01/16: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38527: 02/01/16: Peter Alfke: Re: Repost: Should clock skew be included for setup time analysis?
38537: 02/01/16: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38542: 02/01/17: Allan Herriman: Re: Repost: Should clock skew be included for setup time analysis?
38543: 02/01/17: Ray Andraka: Re: Repost: Should clock skew be included for setup time analysis?
38615: 02/01/19: Philip Freidin: Re: Should clock skew be included for setup time analysis?
38629: 02/01/19: Ray Andraka: Re: Should clock skew be included for setup time analysis?
38633: 02/01/20: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38637: 02/01/20: Hal Murray: Re: Repost: Should clock skew be included for setup time analysis?
38758: 02/01/24: <hamish@cloud.net.au>: Re: Repost: Should clock skew be included for setup time analysis?
38510: 02/01/16: Jonathan Bromley: Re: Repost: Should clock skew be included for setup time analysis?
38515: 02/01/16: Jonathan Bromley: Re: Repost: Should clock skew be included for setup time analysis?
38197: 02/01/08: a_darabiha: Core Generator
38283: 02/01/11: Angel Pino: Re: Core Generator
38530: 02/01/16: a_darabiha: Re: Core Generator
38558: 02/01/17: #BASUKI ENDAH PRIYANTO#: Re: Core Generator
38198: 02/01/08: john: Actel Simulations
38212: 02/01/09: Anthony Ellis: ADPCM?
38224: 02/01/09: Utku Ozcan: Re: ADPCM?
38229: 02/01/09: Austin Lesea: Re: ADPCM?
38564: 02/01/17: Greg Schmid: Re: ADPCM?
38213: 02/01/09: axilon: How can I relate Virtex2 pin names and Slice XY loc?
38235: 02/01/09: Falk Brunner: Re: How can I relate Virtex2 pin names and Slice XY loc?
38239: 02/01/09: Kevin Neilson: Re: How can I relate Virtex2 pin names and Slice XY loc?
38248: 02/01/09: Bret Wade: Re: How can I relate Virtex2 pin names and Slice XY loc?
38379: 02/01/13: Kevin Neilson: Re: How can I relate Virtex2 pin names and Slice XY loc?
38422: 02/01/14: Bret Wade: Re: How can I relate Virtex2 pin names and Slice XY loc?
38401: 02/01/13: Assaf Sarfati: Re: How can I relate Virtex2 pin names and Slice XY loc?
38216: 02/01/09: Matthias Weber: distributed ram bits in XCVxxxx series
38228: 02/01/09: Peter Alfke: Re: distributed ram bits in XCVxxxx series
38255: 02/01/10: Ray Andraka: Re: distributed ram bits in XCVxxxx series
38217: 02/01/09: Matthias Weber: function generators of Xilinx XCVxxxxE series
38238: 02/01/09: John_H: Re: function generators of Xilinx XCVxxxxE series
38218: 02/01/09: k.: bufg instantiation in ISE 4.1
38220: 02/01/09: Allan Herriman: Re: bufg instantiation in ISE 4.1
38260: 02/01/10: k.: Re: bufg instantiation in ISE 4.1
38233: 02/01/09: Andy Peters: Re: bufg instantiation in ISE 4.1
38256: 02/01/10: Ray Andraka: Re: bufg instantiation in ISE 4.1
38257: 02/01/10: Ray Andraka: Re: bufg instantiation in ISE 4.1
38259: 02/01/10: k.: Re: bufg instantiation in ISE 4.1
38361: 02/01/12: <hamish@cloud.net.au>: Re: bufg instantiation in ISE 4.1
38219: 02/01/09: satya: Xilinx XC2000, XC3000, XC4000 families
38223: 02/01/09: Keith R. Williams: Re: Xilinx XC2000, XC3000, XC4000 families
38221: 02/01/09: Richard Padovan: Interpreting Xilinx Timing Analyser report files
38232: 02/01/09: Brian Philofsky: Re: Interpreting Xilinx Timing Analyser report files
38279: 02/01/10: Jay: Re: Interpreting Xilinx Timing Analyser report files
38222: 02/01/09: Hua Wang: comp.arch.fpga : Problem with modelsim and ISE4.1
38234: 02/01/09: Brian Philofsky: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38242: 02/01/09: Rick Filipkiewicz: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38258: 02/01/10: Ray Andraka: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38225: 02/01/09: Markus Meng: Triscend ARM+FPGA chips Experience
38226: 02/01/09: Victor Levandovsky: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
38249: 02/01/10: Philip Cummins: Re: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
38227: 02/01/09: Gacquer William: FPGA and CCD : any experience?
38231: 02/01/09: Jonathan Bromley: Re: FPGA and CCD : any experience?
38245: 02/01/09: Gacquer William: Re: FPGA and CCD : any experience?
38261: 02/01/10: Jonathan Bromley: Re: FPGA and CCD : any experience?
38250: 02/01/09: ikauranen: Re: FPGA and CCD : any experience?
38278: 02/01/10: Jay: Re: FPGA and CCD : any experience?
38309: 02/01/11: M.B.: Re: FPGA and CCD : any experience?
38495: 02/01/15: Jay: Re: FPGA and CCD : any experience?
38241: 02/01/09: rickman: Spartan IIE pinout compatibililty with Virtex E
38243: 02/01/09: Rick Filipkiewicz: Re: Spartan IIE pinout compatibililty with Virtex E
38244: 02/01/09: rickman: Re: Spartan IIE pinout compatibililty with Virtex E
38246: 02/01/09: Han, MT: Where to buy Altera APEX20K with reasonable price?
38247: 02/01/09: Alex Rast: Error -10010 during Digital Buffer Control
38251: 02/01/09: dotty1319: xilinx service pack error
38262: 02/01/10: Santiago de Pablo: [WebPACK or ISE] Mixing Verilog and EDIF?
38358: 02/01/12: <hamish@cloud.net.au>: Re: [WebPACK or ISE] Mixing Verilog and EDIF?
38263: 02/01/10: ssy: Q:Hand placed fast 32 bit barrel shifter for APEX?
38301: 02/01/11: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38306: 02/01/11: ssy: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38328: 02/01/11: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38351: 02/01/11: ssy: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38355: 02/01/12: Ray Andraka: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
38264: 02/01/10: Matthias Scheerer: XST in ISE Alliance 4.1 for Solaris
38267: 02/01/10: Matthias Scheerer: Re: XST in ISE Alliance 4.1 for Solaris
38265: 02/01/10: Herrera, Alfredo [CAR:5T12:EXCH]: coregen in Alliance ISE v4.1i
38268: 02/01/10: Stephan Flock: Re: FPGA Synthesis and implementation
38269: 02/01/10: Ray Andraka: Re: FPGA Synthesis and implementation
38271: 02/01/10: Ray Andraka: Re: FPGA Synthesis and implementation
38329: 02/01/11: H.L: Re: FPGA Synthesis and implementation
38297: 02/01/10: H.L: Re: FPGA Synthesis and implementation
38270: 02/01/10: Matthias Dyer: Avoid routing through a certain area (Xilinx)
38272: 02/01/10: rickman: Re: Avoid routing through a certain area (Xilinx)
38315: 02/01/11: Phil James-Roxby: Re: Avoid routing through a certain area (Xilinx)
38321: 02/01/11: rickman: Re: Avoid routing through a certain area (Xilinx)
38359: 02/01/12: <hamish@cloud.net.au>: Re: Avoid routing through a certain area (Xilinx)
38413: 02/01/14: Christian Plessl: Re: Avoid routing through a certain area (Xilinx)
38430: 02/01/14: Phil James-Roxby: Re: Avoid routing through a certain area (Xilinx)
38281: 02/01/10: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38307: 02/01/11: Christian Plessl: Re: Avoid routing through a certain area (Xilinx)
38308: 02/01/11: Tim: Re: Avoid routing through a certain area (Xilinx)
38320: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38322: 02/01/11: rickman: Re: Avoid routing through a certain area (Xilinx)
38327: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38338: 02/01/11: Bret Wade: Re: Avoid routing through a certain area (Xilinx)
38282: 02/01/11: Angel Pino: EXPAL language ?
38296: 02/01/11: Jim Granville: Re: EXPAL language ?
38318: 02/01/11: Angel Pino: Re: EXPAL language ?
38284: 02/01/10: BM: Xilinx High speed I/O
38312: 02/01/11: Austin Lesea: Re: Xilinx High speed I/O
38319: 02/01/11: Falk Brunner: Re: Xilinx High speed I/O
38285: 02/01/10: H.L: FPGA Synthesis and implementation
38305: 02/01/11: Michael Boehnel: Runtime reconfiguration internals
38323: 02/01/11: Philip Freidin: Re: Runtime reconfiguration internals
38410: 02/01/14: Alex Carreira: Re: Runtime reconfiguration internals
38414: 02/01/14: Michael Boehnel: Re: Runtime reconfiguration internals
38311: 02/01/11: Dan Benson: Help with Older Programmer
38313: 02/01/11: Eric Lukac-Kuruc: Actel Libero for ProAsic in big trouble?
38317: 02/01/11: Timothy R. Sloper: Re: Actel Libero for ProAsic in big trouble?
38324: 02/01/11: rickman: Picking an FPGA
38330: 02/01/11: Austin Lesea: Re: Picking an FPGA
38341: 02/01/11: rickman: Re: Picking an FPGA
38331: 02/01/11: Ray Andraka: Re: Picking an FPGA
38339: 02/01/11: rickman: Re: Picking an FPGA
38352: 02/01/12: Ray Andraka: Re: Picking an FPGA
38380: 02/01/13: rickman: Re: Picking an FPGA
38340: 02/01/11: guy: Re: Picking an FPGA
38353: 02/01/12: Ray Andraka: Re: Picking an FPGA
38364: 02/01/12: rickman: Re: Picking an FPGA
38325: 02/01/11: Steve Holroyd: APEX-II vs VIRTEX-II
38332: 02/01/11: Ray Andraka: Re: APEX-II vs VIRTEX-II
38587: 02/01/18: Steve Holroyd: Re: APEX-II vs VIRTEX-II
38656: 02/01/20: rickman: Re: APEX-II vs VIRTEX-II
39132: 02/02/01: Magnus Homann: Re: APEX-II vs VIRTEX-II
38593: 02/01/18: Mike Treseler: Re: APEX-II vs VIRTEX-II
38740: 02/01/23: Jay: Re: APEX-II vs VIRTEX-II
39181: 02/02/03: Guy Schlacter: Re: APEX-II vs VIRTEX-II
39190: 02/02/04: Russell Shaw: Re: APEX-II vs VIRTEX-II
39720: 02/02/17: rickman: Re: APEX-II vs VIRTEX-II
40084: 02/02/26: Steve Holroyd: Re: APEX-II vs VIRTEX-II
40115: 02/02/27: Austin Lesea: Re: APEX-II vs VIRTEX-II
40165: 02/02/28: Girl: Re: APEX-II vs VIRTEX-II
40167: 02/03/01: Russell Shaw: QuartusII (was Re: APEX-II vs VIRTEX-II)
38326: 02/01/11: Kevin Brace: How to constrain the inputs of a multi-level parity generator and
38335: 02/01/11: Ray Andraka: Re: How to constrain the inputs of a multi-level parity generator and
38444: 02/01/14: Kevin Brace: Re: How to constrain the inputs of a multi-level parity generator and
38333: 02/01/11: Bryan: Xilinx PAR and Editor speed up
38334: 02/01/11: Bryan: Re: Xilinx PAR and Editor speed up
38344: 02/01/11: Duane Clark: Re: Xilinx PAR and Editor speed up
38421: 02/01/14: Bryan: Re: Xilinx PAR and Editor speed up
38426: 02/01/14: Duane Clark: Re: Xilinx PAR and Editor speed up
38363: 02/01/12: Petter Gustad: Re: Xilinx PAR and Editor speed up
38418: 02/01/14: Chandrakiran: Re: Xilinx PAR and Editor speed up
38423: 02/01/14: Bret Wade: Re: Xilinx PAR and Editor speed up
38343: 02/01/11: chris: speech recognition - active noise cancellation
38346: 02/01/12: Kevin Neilson: Re: speech recognition - active noise cancellation
38347: 02/01/11: Jerry Avins: Re: speech recognition - active noise cancellation
38357: 02/01/12: Leon Heller: Re: speech recognition - active noise cancellation
38367: 02/01/12: Jerry Avins: Re: speech recognition - active noise cancellation
38372: 02/01/12: Ray Andraka: Re: speech recognition - active noise cancellation
38373: 02/01/13: Leon Heller: Re: speech recognition - active noise cancellation
38378: 02/01/13: Kevin Neilson: Re: speech recognition - active noise cancellation
38392: 02/01/13: Ray Andraka: Re: speech recognition - active noise cancellation
38434: 02/01/14: Chip Wood: Re: speech recognition - active noise cancellation
38433: 02/01/14: Chip Wood: Re: speech recognition - active noise cancellation
38350: 02/01/12: Ray Andraka: Re: speech recognition - active noise cancellation
38368: 02/01/12: david garnett: Re: speech recognition - active noise cancellation
38405: 02/01/14: Raman Arora: Re: speech recognition - active noise cancellation
38356: 02/01/11: Balakrishnan: FPGA : Configurtion
38366: 02/01/12: C.Schlehaus: Re: FPGA : Configurtion
38360: 02/01/11: balakrishnan: FPGA configuration
38381: 02/01/13: rickman: Re: FPGA configuration
38388: 02/01/13: z.karim: Re: FPGA configuration
38398: 02/01/13: rickman: Re: FPGA configuration
38370: 02/01/12: Adam Elbirt: Quick question regarding IEEE-TVLSI and IEEE-Computer
38374: 02/01/12: llossak: modelsim
38390: 02/01/13: Rick Filipkiewicz: Re: modelsim
38375: 02/01/12: ssy: the timng of the lpm_fifo
38382: 02/01/13: rickman: Re: MSP430 + Xilinx via JTAG
38400: 02/01/13: DG_1: Re: MSP430 + Xilinx via JTAG
38403: 02/01/14: rickman: Re: MSP430 + Xilinx via JTAG
38451: 02/01/15: DG_1: Re: MSP430 + Xilinx via JTAG
38852: 02/01/26: DG_1: Re: MSP430 + Xilinx via JTAG
38874: 02/01/27: rickman: Re: MSP430 + Xilinx via JTAG
39046: 02/01/30: Elizabeth D. Rather: Re: MSP430 + Xilinx via JTAG
39130: 02/02/01: rickman: Re: MSP430 + Xilinx via JTAG
39182: 02/02/03: rickman: Re: MSP430 + Xilinx via JTAG
39282: 02/02/05: Elizabeth D. Rather: Re: MSP430 + Xilinx via JTAG
38847: 02/01/26: rickman: Re: MSP430 + Xilinx via JTAG
38420: 02/01/14: Damir Danijel Zagar: Re: MSP430 + Xilinx via JTAG
38449: 02/01/15: DG_1: Re: MSP430 + Xilinx via JTAG
38477: 02/01/15: Geir Atle Ward: Re: MSP430 + Xilinx via JTAG
38552: 02/01/17: Damir Danijel Zagar: Re: MSP430 + Xilinx via JTAG
38856: 02/01/26: Matti Ruusunen: Re: MSP430 + Xilinx via JTAG
38872: 02/01/27: rickman: Re: MSP430 + Xilinx via JTAG
38881: 02/01/27: Matti Ruusunen: Re: MSP430 + Xilinx via JTAG
38383: 02/01/13: TonyS2: FS xilinx 963//Data I/O 2900 Programmers
38384: 02/01/13: David Findlay: Homebrew computers using FPGA?
38385: 02/01/13: Falk Brunner: Re: Homebrew computers using FPGA?
38396: 02/01/13: Jan Gray: Re: Homebrew computers using FPGA?
38386: 02/01/13: cn99: Re: Homebrew computers using FPGA?
38391: 02/01/13: Ray Andraka: Re: Homebrew computers using FPGA?
38399: 02/01/13: David Findlay: Re: Homebrew computers using FPGA?
38402: 02/01/14: Peter Ormsby: Re: Homebrew computers using FPGA?
38416: 02/01/14: David Findlay: Re: Homebrew computers using FPGA?
38854: 02/01/26: Franck Pissotte: Re: Homebrew computers using FPGA?
38954: 02/01/28: Eric Smith: Re: Homebrew computers using FPGA?
38393: 02/01/13: Duane Clark: Re: Homebrew computers using FPGA?
38461: 02/01/15: Herbert Kleebauer: Re: Homebrew computers using FPGA?
38395: 02/01/13: Peter Ormsby: Re: Homebrew computers using FPGA?
38437: 02/01/14: Andy Ray: Re: Homebrew computers using FPGA?
38397: 02/01/14: Jim Granville: Re: Homebrew computers using FPGA?
38855: 02/01/26: Franck Pissotte: Re: Homebrew computers using FPGA?
38900: 02/01/28: Rob Finch: Re: Homebrew computers using FPGA?
38404: 02/01/14: Antonio: CLKDLL cascade questions
38428: 02/01/14: Falk Brunner: Re: CLKDLL cascade questions
38463: 02/01/15: <hamish@cloud.net.au>: Re: CLKDLL cascade questions
38472: 02/01/15: Austin Lesea: Re: CLKDLL cascade questions
38446: 02/01/15: Peter Alfke: Re: CLKDLL cascade questions
38406: 02/01/14: Antonio: .sdf question
38409: 02/01/14: Ansgar Bambynek: Re: .sdf question
38455: 02/01/15: Rick Filipkiewicz: Re: .sdf question
38407: 02/01/14: balakrishnan: SPARTAN-XL CONFIGURTAION
38573: 02/01/17: Yury: Re: SPARTAN-XL CONFIGURTAION
38408: 02/01/14: grohss: variable declare
38439: 02/01/14: Andy Ray: Re: variable declare
38500: 02/01/15: Jay: Re: variable declare
38411: 02/01/14: Martin Fischer: Falling edge in PLD
38427: 02/01/14: Falk Brunner: Re: Falling edge in PLD
38450: 02/01/15: David Miller: Re: Falling edge in PLD
38456: 02/01/15: Rick Filipkiewicz: Re: Falling edge in PLD
38464: 02/01/15: <hamish@cloud.net.au>: Re: Falling edge in PLD
38452: 02/01/15: Thomas Stanka: Re: Falling edge in PLD
38459: 02/01/15: Martin Fischer: Re: Falling edge in PLD
38479: 02/01/15: Falk Brunner: Re: Falling edge in PLD
38412: 02/01/14: Philippe Robert: Hard macro for Xilinx FPGA
38481: 02/01/15: Bret Wade: Re: Hard macro for Xilinx FPGA
38417: 02/01/14: Antonio: Some Aldec Questions
38419: 02/01/14: Philippe Robert: test
38424: 02/01/14: Steven Menk: Synthesis: Protel 99SE to XC2S200
38505: 02/01/16: z.karim: Re: Synthesis: Protel 99SE to XC2S200
38519: 02/01/16: <hamish@cloud.net.au>: Re: Synthesis: Protel 99SE to XC2S200
38425: 02/01/14: Rodolfo Jardim de Azevedo: Leonardo + Xilinx tools help
38436: 02/01/14: Mike Treseler: Re: Leonardo + Xilinx tools help
38489: 02/01/15: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38492: 02/01/15: Mike Treseler: Re: Leonardo + Xilinx tools help
38520: 02/01/16: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38524: 02/01/16: Mike Treseler: Re: Leonardo + Xilinx tools help
38525: 02/01/16: Mike Treseler: Re: Leonardo + Xilinx tools help
38538: 02/01/16: Ray Andraka: Re: Leonardo + Xilinx tools help
38553: 02/01/17: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38566: 02/01/17: Mike Treseler: Re: Leonardo + Xilinx tools help
38560: 02/01/17: newman: Re: Leonardo + Xilinx tools help
38442: 02/01/14: Tom Dillon: Re: Leonardo + Xilinx tools help
38491: 02/01/15: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38509: 02/01/16: Nicolas Matringe: Re: Leonardo + Xilinx tools help
38518: 02/01/16: Rodolfo Jardim de Azevedo: Re: Leonardo + Xilinx tools help
38521: 02/01/16: Nicolas Matringe: Re: Leonardo + Xilinx tools help
38429: 02/01/14: Falk Brunner: Radiation Resistance
38432: 02/01/14: Austin Lesea: Re: Radiation Resistance
38484: 02/01/15: Falk Brunner: Re: Radiation Resistance
38435: 02/01/14: H.L: Synthesis in FPGA Express
38504: 02/01/16: z.karim: Re: Synthesis in FPGA Express
38511: 02/01/16: H.L: Re: Synthesis in FPGA Express
38523: 02/01/16: Jay: Re: Synthesis in FPGA Express
38438: 02/01/14: Seb: Insight eval board: i/o problem
38443: 02/01/14: Angel Pino: PAL Express Language
38445: 02/01/14: kossyma: how do i implement it?
38457: 02/01/15: Rick Filipkiewicz: Re: how do i implement it?
38447: 02/01/15: ÀÌÃá¿ë: SDH Pointer generator and Pointer interpreter
38480: 02/01/15: Falk Brunner: Re: SDH Pointer generator and Pointer interpreter
38448: 02/01/14: strut911: SYN_HIER attribute in synplify v7.0
38499: 02/01/15: Jay: Re: SYN_HIER attribute in synplify v7.0
38453: 02/01/15: kossyma: remainder
38471: 02/01/15: luigi funes: Re: remainder
38503: 02/01/16: z.karim: Re: remainder
38498: 02/01/15: Jay: Re: remainder
38454: 02/01/15: Madhura Bokil: FPGA : VHDL netlist for simulation
38502: 02/01/16: z.karim: Re: FPGA : VHDL netlist for simulation
38458: 02/01/15: Rick Filipkiewicz: Synplify and CoolRunner - Help
38460: 02/01/15: Rick Filipkiewicz: Re: Synplify and CoolRunner - Help
38462: 02/01/15: Andreas Kugel: Virtex-2 Frequency Synhtesis
38473: 02/01/15: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38482: 02/01/15: Rick Filipkiewicz: Re: Virtex-2 Frequency Synhtesis
38486: 02/01/15: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38540: 02/01/17: Rick Filipkiewicz: Re: Virtex-2 Frequency Synhtesis
38541: 02/01/16: Austin Lesea: Re: Virtex-2 Frequency Synhtesis
38467: 02/01/15: Bernd Scheuermann: RS232 on Atmel ATSTK40 board
38470: 02/01/15: Jan Pech: Re: RS232 on Atmel ATSTK40 board
38476: 02/01/15: Bernd Scheuermann: Re: RS232 on Atmel ATSTK40 board
38483: 02/01/15: Dave Vanden Bout: Re: RS232 on Atmel ATSTK40 board
38468: 02/01/15: Petter Gustad: Xilinx XC4003A-6, docs and tools?
38469: 02/01/15: Russell Tessier: FPGA'2002: Early Registration Deadline
38474: 02/01/15: Richard Auletta: ASIC 2002 Call For Papers
38550: 02/01/17: Paulo Valentim: Re: ASIC 2002 Call For Papers
38478: 02/01/16: Daniel Yap: Altera Compiling Error..WHY?????
38487: 02/01/15: Alan Nishioka: Re: Altera Compiling Error..WHY?????
38493: 02/01/15: Mike Treseler: Re: Altera Compiling Error..WHY?????
38496: 02/01/15: Jay: Re: Altera Compiling Error..WHY?????
38497: 02/01/15: Guy Schlacter: Re: Altera Compiling Error..WHY?????
38485: 02/01/15: Annette Van Benthum: Flexbus and Altera
38494: 02/01/15: David Rogoff: path for Vital component in assert?
38934: 02/01/28: Brian Philofsky: Re: path for Vital component in assert?
38506: 02/01/15: Antonio: A strange Xilinx 4.1 parser error
38507: 02/01/15: Antonio: Xilinx 4.1 Implementation report questions
38590: 02/01/18: Brian Philofsky: Re: Xilinx 4.1 Implementation report questions
38508: 02/01/15: Antonio: Xilinx Timing report question
38743: 02/01/23: Jay: Re: Xilinx Timing report question
38512: 02/01/16: Christian Lehmann: info about NIOS softcore processor
38513: 02/01/16: Wolfgang Loewer: Re: info about NIOS softcore processor
38522: 02/01/16: Simon Fisher: Audio time delay circuit
38526: 02/01/16: Peter Alfke: Re: Audio time delay circuit
38528: 02/01/16: Falk Brunner: Re: Audio time delay circuit
38531: 02/01/16: Leon Heller: Re: Audio time delay circuit
38563: 02/01/17: Kevin Neilson: Re: Audio time delay circuit
38565: 02/01/17: Leon Heller: Re: Audio time delay circuit
38568: 02/01/17: Eric Smith: Re: Audio time delay circuit
38569: 02/01/17: Peter Alfke: Re: Audio time delay circuit
38571: 02/01/17: Eric Smith: Re: Audio time delay circuit
38574: 02/01/18: Peter Alfke: Re: Audio time delay circuit
38578: 02/01/18: Simon Fisher: Re: Audio time delay circuit
38592: 02/01/18: Kevin Neilson: Re: Audio time delay circuit
38595: 02/01/18: Falk Brunner: Re: Audio time delay circuit
38634: 02/01/19: tony: Re: Audio time delay circuit
38598: 02/01/18: Ray Andraka: Re: Audio time delay circuit
38600: 02/01/18: Georg Acher: Re: Audio time delay circuit
38603: 02/01/19: Jim Granville: Re: Audio time delay circuit
38627: 02/01/19: Ray Andraka: Re: Audio time delay circuit
38625: 02/01/19: Ray Andraka: Re: Audio time delay circuit
38779: 02/01/25: Andy Peters: Re: Audio time delay circuit
38781: 02/01/25: Ray Andraka: Re: Audio time delay circuit
38782: 02/01/24: Peter Alfke: Re: Audio time delay circuit
38529: 02/01/16: Andrew Ha: I2C multiplexer
38606: 02/01/18: Randy Bolling: Re: I2C multiplexer
38613: 02/01/19: AH: Re: I2C multiplexer
38739: 02/01/23: Carl Brannen: Re: I2C multiplexer
38532: 02/01/16: a_darabiha: Image Processing on FPGAs. Dose System Generator help??
38567: 02/01/17: Ray Andraka: Re: Image Processing on FPGAs. Dose System Generator help??
38707: 02/01/22: Niall Battson: Re: Image Processing on FPGAs. Dose System Generator help??
38533: 02/01/16: a_darabiha: SysGen on PC / Unix ?
38534: 02/01/16: Amit Thakar: Signal processing using FPGAs
38535: 02/01/16: Austin Lesea: Re: Signal processing using FPGAs
38536: 02/01/16: Ray Andraka: Re: Signal processing using FPGAs
38561: 02/01/17: Falk Brunner: Re: Signal processing using FPGAs
38661: 02/01/21: Ron Huizen: Re: Signal processing using FPGAs
38669: 02/01/21: Ray Andraka: Re: Signal processing using FPGAs
38539: 02/01/16: Amit Thakar: Re: Signal processing using FPGAs
38556: 02/01/17: Austin Lesea: Re: Signal processing using FPGAs
38544: 02/01/17: Steve Underwood: Re: Signal processing using FPGAs
38546: 02/01/17: Bert Cuzeau: Re: Signal processing using FPGAs
38570: 02/01/18: #BASUKI ENDAH PRIYANTO#: RE: Signal processing using FPGAs
38668: 02/01/21: glen herrmannsfeldt: Re: Signal processing using FPGAs
38675: 02/01/21: Peter Alfke: Re: Signal processing using FPGAs
38680: 02/01/21: Eric Smith: Re: Signal processing using FPGAs
38681: 02/01/21: Peter Alfke: Re: Signal processing using FPGAs
38700: 02/01/22: John_H: Re: Signal processing using FPGAs
38683: 02/01/22: Ray Andraka: Re: Signal processing using FPGAs
38545: 02/01/17: David A Hand: How to set PROM package in ISE 4.1 ?
38547: 02/01/17: Christian Plessl: Virtex2 ICAP
38557: 02/01/17: Austin Lesea: Re: Virtex2 ICAP
38559: 02/01/17: Christian Plessl: Re: Virtex2 ICAP
38549: 02/01/17: hoothsb: how should i change it?
38551: 02/01/17: adrian: Too many errors
38555: 02/01/17: Brad Eckert: CoreGen question
38562: 02/01/17: Speedy Zero Two: Re: CoreGen question
38591: 02/01/18: Brad Eckert: Re: CoreGen question
38596: 02/01/18: Falk Brunner: Re: CoreGen question
38572: 02/01/17: Yury: Coregen Half-Band FIR filter implemenation does not work
38582: 02/01/18: newman: Re: Coregen Half-Band FIR filter implemenation does not work
38597: 02/01/18: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
39757: 02/02/19: Chris Dick: Re: Coregen Half-Band FIR filter implemenation does not work
39791: 02/02/19: newman: Re: Coregen Half-Band FIR filter implemenation does not work
39796: 02/02/19: Clark Pope: Re: Coregen Half-Band FIR filter implemenation does not work
38780: 02/01/25: Andy Peters: Re: Coregen Half-Band FIR filter implemenation does not work
38815: 02/01/25: Clark Pope: Re: Coregen Half-Band FIR filter implemenation does not work
38850: 02/01/26: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
38818: 02/01/25: Yury: Re: Coregen Half-Band FIR filter implemenation does not work
38870: 02/01/26: newman: Re: Coregen Half-Band FIR filter implemenation does not work
38876: 02/01/27: Rick Filipkiewicz: Re: Coregen Half-Band FIR filter implemenation does not work
39085: 02/01/31: <news@rtrussell.co.uk>: Re: Coregen Half-Band FIR filter implemenation does not work
38575: 02/01/17: chandrakiran Verma: Floorplanning :Problem in floorplanning
38576: 02/01/17: dotty1319: service pack8 can't use
38577: 02/01/18: H.L: Re: service pack8 can't use
38602: 02/01/18: rs: Re: service pack8 can't use
38579: 02/01/18: Benn: verilog/vhdl codeing style
38583: 02/01/18: Pallek, Andrew [CAR:CN34:EXCH]: Re: verilog/vhdl codeing style
38621: 02/01/19: VhdlCohen: Re: verilog/vhdl codeing style
38580: 02/01/18: Juergen Buehler: DDR-Interface
38581: 02/01/18: Paul Baxter: Re: DDR-Interface
38588: 02/01/18: Juergen Buehler: Re: DDR-Interface
38584: 02/01/18: Roberta Crescentini: Re: DDR-Interface
38586: 02/01/18: Austin Lesea: Re: DDR-Interface
38663: 02/01/21: Edward Moore: Re: DDR-Interface
40460: 02/03/07: Manfred Kraus: Re: DDR-Interface
38585: 02/01/18: Paul: Quartus 2 and bus ripping
38658: 02/01/21: Paul: Re: Quartus 2 and bus ripping
38666: 02/01/21: Mike Treseler: Re: Quartus 2 and bus ripping
38671: 02/01/21: Paul: Re: Quartus 2 and bus ripping
38678: 02/01/21: Steen Larsen: Re: Quartus 2 and bus ripping
38688: 02/01/22: Paul: Re: Quartus 2 and bus ripping
38733: 02/01/23: Paul: Re: Quartus 2 and bus ripping
38962: 02/01/28: Steen Larsen: Re: Quartus 2 and bus ripping
38972: 02/01/29: Paul: Re: Quartus 2 and bus ripping
38589: 02/01/18: Steve Holroyd: Fast LVDS Backplanes
38594: 02/01/19: Daniel Yap: why Altera LPM_ROM can't drive out value?
38601: 02/01/18: rs: VirtexII ES configuration
38604: 02/01/18: Austin Lesea: Re: VirtexII ES configuration
38619: 02/01/19: rs: Re: VirtexII ES configuration
38605: 02/01/18: Randy Bolling: Re: VirtexII ES configuration
38607: 02/01/18: Kevin Goodsell: Simple shift register not working
38610: 02/01/18: Brian Philofsky: Re: Simple shift register not working
38639: 02/01/20: Kevin Goodsell: Re: Simple shift register not working
38628: 02/01/19: Ray Andraka: Re: Simple shift register not working
38638: 02/01/20: Kevin Goodsell: Re: Simple shift register not working
38742: 02/01/23: Jay: Re: Simple shift register not working
38748: 02/01/23: spyng: Re: Simple shift register not working
38849: 02/01/26: Kevin Goodsell: Re: Simple shift register not working (update)
38889: 02/01/27: newman: Re: Simple shift register not working (update)
38931: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38932: 02/01/28: Peter Alfke: Re: Simple shift register not working (update)
38935: 02/01/28: Ray Andraka: Re: Simple shift register not working (update)
38936: 02/01/28: Bob Perlman: Re: Simple shift register not working (update)
38940: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38965: 02/01/28: newman: Re: Simple shift register not working (update)
38891: 02/01/28: Bob Perlman: Re: Simple shift register not working (update)
38941: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38893: 02/01/28: Ray Andraka: Re: Simple shift register not working (update)
38943: 02/01/28: Kevin Goodsell: Re: Simple shift register not working (update)
38896: 02/01/28: Peter Alfke: Re: Simple shift register not working (update)
38608: 02/01/18: Joe: Shift Register question
38611: 02/01/19: Kevin Neilson: Re: Shift Register question
38614: 02/01/19: JoeG: Re: Shift Register question
38624: 02/01/19: Ray Andraka: Re: Shift Register question
38626: 02/01/19: JoeG: Re: Shift Register question
38609: 02/01/18: Burnett: microcontroller manager question
38769: 02/01/24: Santiago de Pablo: Re: microcontroller manager question
38616: 02/01/19: Benni: initial value
38617: 02/01/19: Benn: Re: initial value
38620: 02/01/19: VhdlCohen: Re: initial value
38618: 02/01/19: Benny: Re: initial value
38623: 02/01/19: AMID GUBTA: Re: initial value
38631: 02/01/19: Benn: Re: initial value
38632: 02/01/19: Benn: Re: initial value
38622: 02/01/19: Mechanic Mike: Dev tools needed
38630: 02/01/19: Paddy Mullan: JBits: Partial Reconfiguration
38654: 02/01/20: Alex Carreira: Re: JBits: Partial Reconfiguration
38635: 02/01/19: tony: FS VME BUS Cages ELMA
38636: 02/01/19: Benny: help me!
38653: 02/01/20: newman: Re: help me!
38655: 02/01/20: Benny: Re: help me!
38667: 02/01/21: Davis Moore (nospam): Re: help me!
38672: 02/01/21: Hicks: Re: help me!
38673: 02/01/21: Brian Philofsky: Re: help me!
38674: 02/01/21: Davis Moore (nospam): Re: help me!
38676: 02/01/21: Hicks: Re: help me!
38679: 02/01/21: Davis Moore (nospam): Re: help me!
38684: 02/01/21: Theron Hicks (Terry): Re: help me!
38696: 02/01/22: Theron Hicks: Re: help me!
38691: 02/01/22: newman: Re: help me!
38640: 02/01/20: Bolis: Nios development kit
38641: 02/01/20: Bolis: Re: Nios development kit
38642: 02/01/20: James Srinivasan: Re: Nios development kit
38643: 02/01/20: James Srinivasan: Altera Nios v2
38646: 02/01/20: Victor Schutte: Re: Altera Nios v2
38647: 02/01/20: James Srinivasan: Re: Altera Nios v2
38652: 02/01/20: Peter Ormsby: Re: Altera Nios v2
38771: 02/01/24: Alan Calac: Re: Altera Nios v2
38772: 02/01/24: James Srinivasan: Re: Altera Nios v2
38644: 02/01/20: strut911: is it possible to floorplan a module and lock it down?
38645: 02/01/20: strut911: bottom up synthesis with synplicity?
38657: 02/01/20: Assaf Sarfati: Re: bottom up synthesis with synplicity?
38660: 02/01/21: Rick Filipkiewicz: Re: bottom up synthesis with synplicity?
38648: 02/01/20: sitaram: SPARTAN 2-DLL USAGE
38649: 02/01/20: sitaram: Re: SPARTAN 2-DLL USAGE
38651: 02/01/20: Peter Alfke: Re: SPARTAN 2-DLL USAGE
38664: 02/01/21: Austin Lesea: Re: SPARTAN 2-DLL USAGE
38650: 02/01/20: Richard B. Katz: CFP: 5th Annual MAPLD International Conference
38662: 02/01/21: Andrej Jancura: Atmel FPGA configuration memory?!
38670: 02/01/21: Peter Alfke: Re: Atmel FPGA configuration memory?!
38677: 02/01/21: Ulf Samuelsson: Re: Atmel FPGA configuration memory?!
38685: 02/01/22: DG_1: Re: Atmel FPGA configuration memory?!
38689: 02/01/22: Andrej Jancura: Re: Atmel FPGA configuration memory?!
38705: 02/01/22: Ulf Samuelsson: Re: Atmel FPGA configuration memory?!
38726: 02/01/23: Andrej Jancura: Re: Atmel FPGA configuration memory?!
38751: 02/01/24: Hal Murray: Re: Atmel FPGA configuration memory?!
38756: 02/01/24: Andrej Jancura: Re: Atmel FPGA configuration memory?!
38832: 02/01/26: Hal Murray: Re: Atmel FPGA configuration memory?!
38686: 02/01/21: ssy: Q: can ROM content affect logic syn result
38692: 02/01/22: newman: Re: Q: can ROM content affect logic syn result
38693: 02/01/22: Allan Herriman: Re: Q: can ROM content affect logic syn result
38694: 02/01/22: Ray Andraka: Re: Q: can ROM content affect logic syn result
38701: 02/01/22: sunny: Re: Q: can ROM content affect logic syn result
38734: 02/01/23: Jay: Re: Q: can ROM content affect logic syn result
38737: 02/01/23: Ray Andraka: Re: Q: can ROM content affect logic syn result
38752: 02/01/24: ssy: Re: Q: can ROM content affect logic syn result
38687: 02/01/22: X. Q.: Gate level simu in ModelSim.
38699: 02/01/22: Brian Philofsky: Re: Gate level simu in ModelSim.
38690: 02/01/22: David de =?iso-8859-1?Q?Andr=E9s Mart=EDnez?=: XSV800 video decoder (SAA7113) programming
38697: 02/01/22: Hicks: effective high resolution counter using DLL clock phases
38750: 02/01/24: Hal Murray: Re: effective high resolution counter using DLL clock phases
38702: 02/01/22: Gunther May: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38732: 02/01/23: Gunther May: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38738: 02/01/23: Ray Andraka: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38757: 02/01/24: jcding: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38703: 02/01/22: ray.frost: vhdl code example required - x186 uC bus interfacing
38704: 02/01/22: Theron Hicks: analog input via serial connection
38706: 02/01/22: Ray Andraka: Re: analog input via serial connection
38708: 02/01/22: Theron Hicks: Re: analog input via serial connection
38710: 02/01/22: laars kumar: Access to http://ripem.msu.edu
38711: 02/01/23: Hristo Stevic: input source to feed 20 filters! how to decrease the load
38712: 02/01/23: Ray Andraka: Re: input source to feed 20 filters! how to decrease the load
38713: 02/01/22: Peter Alfke: Re: input source to feed 20 filters! how to decrease the load
38727: 02/01/23: Hristo Stevic: Re: input source to feed 20 filters! how to decrease the load
38714: 02/01/22: beav: Virtex-II Programming Highs and Lows
38715: 02/01/23: strut911: Re: Virtex-II Programming Highs and Lows
38716: 02/01/23: Bob Perlman: Re: Virtex-II Programming Highs and Lows
38721: 02/01/23: Ray Andraka: Re: Virtex-II Programming Highs and Lows
38718: 02/01/23: uttam singh: Internal tri state buffer..
38725: 02/01/23: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Internal tri state buffer..
38741: 02/01/23: Ray Andraka: Re: Internal tri state buffer..
38760: 02/01/24: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Internal tri state buffer..
38764: 02/01/24: Ray Andraka: Re: Internal tri state buffer..
38719: 02/01/23: jcding: Analog input into Altera FLEX10K using ADC. Can anyone help??
38761: 02/01/24: Bert Cuzeau: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38787: 02/01/25: Bert Cuzeau: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38789: 02/01/25: jcding: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38722: 02/01/23: Muthu: Handling the events below in verilog coding??
38724: 02/01/23: Josan Moreno: Post-synthesis simulation with Modelsim from Leonardo Netlist
38728: 02/01/23: Robert S. Grimes: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
38729: 02/01/23: Kamal Patel: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
38730: 02/01/23: Robert S. Grimes: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
38744: 02/01/23: Dave Vanden Bout: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
38731: 02/01/23: AP: IDT7204 Using CoreGen
38735: 02/01/23: Peter Alfke: Re: IDT7204 Using CoreGen
38766: 02/01/24: Phil Connor: Re: IDT7204 Using CoreGen
38768: 02/01/24: AP: Re: IDT7204 Using CoreGen
38745: 02/01/23: Burnett: boot manager
38747: 02/01/23: Mike Treseler: Re: boot manager
38746: 02/01/24: Speedy: NTSC/IEEE1394 input to VGA output in FPGA, with overlay
38749: 02/01/24: Victor Schutte: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
38754: 02/01/24: Nial Stewart: Re: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
38796: 02/01/25: Victor Schutte: Re: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
38753: 02/01/24: Mark Kinsley: Intel vs. AMD
38792: 02/01/25: Martin Thompson: Re: Intel vs. AMD
38807: 02/01/25: Mark Kinsley: Re: Intel vs. AMD
38797: 02/01/25: Ensign Jimmy: Re: Intel vs. AMD
38804: 02/01/25: Rick Filipkiewicz: Re: Intel vs. AMD
39069: 02/01/31: Russell Shaw: Re: Intel vs. AMD
39070: 02/01/31: VR: Re: Intel vs. AMD
39116: 02/01/31: emanuel stiebler: Re: Intel vs. AMD
39150: 02/02/02: VR: Re: Intel vs. AMD
38755: 02/01/24: Markus Meng: UCF Parsing Error for Pin2Pin Constraints 3.1i
38759: 02/01/24: Fong Chii Biao: Dynamic Reconfiguration of single Xilinx FPGA
38762: 02/01/24: Alex Carreira: Re: Dynamic Reconfiguration of single Xilinx FPGA
38765: 02/01/24: Ray Andraka: Re: Dynamic Reconfiguration of single Xilinx FPGA
38770: 02/01/25: Fong Chii Biao: Re: Dynamic Reconfiguration of single Xilinx FPGA
38773: 02/01/24: Ray Andraka: Re: Dynamic Reconfiguration of single Xilinx FPGA
38783: 02/01/25: Fong Chii Biao: Re: Dynamic Reconfiguration of single Xilinx FPGA
38785: 02/01/25: Ray Andraka: Re: Dynamic Reconfiguration of single Xilinx FPGA
38767: 02/01/25: Fong Chii Biao: Re: Dynamic Reconfiguration of single Xilinx FPGA
38939: 02/01/28: Alex Carreira: Re: Dynamic Reconfiguration of single Xilinx FPGA
38777: 02/01/24: Peter Alfke: Re: Dynamic Reconfiguration of single Xilinx FPGA
38784: 02/01/25: Fong Chii Biao: Re: Dynamic Reconfiguration of single Xilinx FPGA
38801: 02/01/25: Philip Freidin: Re: Dynamic Reconfiguration of single Xilinx FPGA
39042: 02/01/30: Steve Casselman: Re: Dynamic Reconfiguration of single Xilinx FPGA
39056: 02/01/30: Peter Alfke: Re: Dynamic Reconfiguration of single Xilinx FPGA
38763: 02/01/24: Jan Gray: Re: www.fpga.org
38774: 02/01/24: Deli Geng (David): Does Xilinx Spartan-II have reserved pin for PCI?
38778: 02/01/24: Eric Crabill: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38808: 02/01/25: Kevin Brace: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38842: 02/01/26: Deli Geng (David): Re: Does Xilinx Spartan-II have reserved pin for PCI?
38848: 02/01/26: Kevin Brace: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38775: 02/01/24: Shawn: Synthsis Tools for Xilinx
38776: 02/01/24: Ray Andraka: Re: Synthsis Tools for Xilinx
38791: 02/01/25: Andreas Roland: Re: Synthsis Tools for Xilinx
38813: 02/01/25: Kevin Brace: Re: Synthsis Tools for Xilinx
38824: 02/01/26: Russell Shaw: Re: Synthsis Tools for Xilinx
38829: 02/01/26: Kevin Brace: Re: Synthsis Tools for Xilinx
38833: 02/01/26: Paul: Re: Synthesis Tools for Xilinx
38851: 02/01/26: Kevin Brace: Re: Synthesis Tools for Xilinx
38834: 02/01/26: Russell Shaw: Re: Synthsis Tools for Xilinx
38859: 02/01/26: Matt Bielstein: Re: Synthsis Tools for Xilinx
38997: 02/01/29: Mark Kinsley: Re: Synthsis Tools for Xilinx
38786: 02/01/24: Con Cac: www.fpga.org
38788: 02/01/25: Mark Barr: Get error that part is invalid or not supported when Run from synthesis
38830: 02/01/26: Kevin Brace: Re: Get error that part is invalid or not supported when Run from
38790: 02/01/25: Paul: Question on synthesis
38793: 02/01/25: Russell Shaw: Xilinx webpack
38803: 02/01/25: Falk Brunner: Re: Xilinx webpack
38822: 02/01/26: Russell Shaw: Re: Xilinx webpack
38831: 02/01/26: Hal Murray: Re: Xilinx webpack
38844: 02/01/26: Rick Filipkiewicz: Re: Xilinx webpack
38840: 02/01/26: Falk Brunner: Re: Xilinx webpack
38861: 02/01/27: Russell Shaw: Re: Xilinx webpack
38863: 02/01/26: Kevin Brace: Re: Xilinx webpack
38865: 02/01/27: Peter Alfke: Re: Xilinx webpack
38877: 02/01/27: Rick Filipkiewicz: Re: Xilinx webpack
38884: 02/01/27: Peter Alfke: Re: Xilinx webpack
38880: 02/01/27: Russell Shaw: Re: Xilinx webpack
38882: 02/01/27: Peter Alfke: Re: Xilinx webpack
38883: 02/01/27: Rick Filipkiewicz: Re: Xilinx webpack
38960: 02/01/29: Jim Granville: Re: Xilinx webpack
38967: 02/01/29: Rick Filipkiewicz: Re: Xilinx webpack
38968: 02/01/29: Tim: Re: Xilinx webpack
38887: 02/01/28: Russell Shaw: Re: Xilinx webpack
38888: 02/01/28: Russell Shaw: Re: Xilinx webpack
38894: 02/01/28: Kevin Brace: Re: Xilinx webpack
38919: 02/01/28: Ray Andraka: Re: Xilinx webpack
38897: 02/01/28: Peter Alfke: Re: Xilinx webpack
38909: 02/01/28: Russell Shaw: Re: Xilinx webpack
38910: 02/01/28: Paul: Re: Xilinx webpack
38924: 02/01/28: Peter Alfke: Re: Xilinx webpack
38928: 02/01/28: Falk Brunner: Re: Xilinx webpack
38947: 02/01/28: Ray Andraka: Re: Xilinx webpack
39013: 02/01/30: Philip Freidin: Re: Xilinx webpack
38952: 02/01/28: Russell Shaw: Re: Xilinx webpack
38957: 02/01/29: Jim Granville: Re: Xilinx webpack
38961: 02/01/29: Tim: Re: Xilinx webpack
38966: 02/01/28: Keith R. Williams: Re: Xilinx webpack
38825: 02/01/26: Russell Shaw: Re: Xilinx webpack
38841: 02/01/26: Falk Brunner: Re: Xilinx webpack
38811: 02/01/25: Kevin Brace: Re: Xilinx webpack
38821: 02/01/26: Russell Shaw: Re: Xilinx webpack
38794: 02/01/25: Markus Wannemacher: XC2V10000 still on the Xilinx roadmap?
38799: 02/01/25: newman: Re: XC2V10000 still on the Xilinx roadmap?
38926: 02/01/28: Austin Lesea: Re: XC2V10000 still on the Xilinx roadmap?
38795: 02/01/25: Markus Meng: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38798: 02/01/25: John_H: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38814: 02/01/26: John_H: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38816: 02/01/26: Ray Andraka: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38819: 02/01/25: John Handwork: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38828: 02/01/26: Ray Andraka: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38800: 02/01/25: Kevin Brace: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38802: 02/01/25: Chris: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38806: 02/01/25: Markus Meng: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38810: 02/01/25: Kevin Brace: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38809: 02/01/25: newman: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38805: 02/01/25: Jeroen Van den Keybus: Pin assignment on ACEX1K
38812: 02/01/25: Kevin Brace: Re: Pin assignment on ACEX1K
38835: 02/01/26: Martin Schoeberl: Re: Pin assignment on ACEX1K
38903: 02/01/28: heyho: Re: Pin assignment on ACEX1K
38918: 02/01/28: Ray Andraka: Re: Pin assignment on ACEX1K
38942: 02/01/28: Kevin Brace: Re: Pin assignment on ACEX1K
39011: 02/01/29: rickman: Re: Pin assignment on ACEX1K
39016: 02/01/30: Kevin Brace: Re: Pin assignment on ACEX1K
39129: 02/02/01: rickman: Re: Pin assignment on ACEX1K
38978: 02/01/29: Jeroen Van den Keybus: Re: Pin assignment on ACEX1K
39015: 02/01/29: Kevin Brace: Re: Pin assignment on ACEX1K
39139: 02/02/01: Marco Serafini: Re: Pin assignment on ACEX1K
39238: 02/02/04: Jay: Re: Pin assignment on ACEX1K
38817: 02/01/26: David Miller: Xilinx PCI logicore: clarification on nature of COMPLETE
38820: 02/01/25: Kevin Brace: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38866: 02/01/27: David Miller: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38869: 02/01/26: Eric Crabill: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38885: 02/01/27: Mike Johnson: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38898: 02/01/28: Kevin Brace: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38823: 02/01/26: Chatpapon Prasartsee: Mapping between Xlinx 4K and Spartan-II
38827: 02/01/26: Ray Andraka: Re: Mapping between Xlinx 4K and Spartan-II
38836: 02/01/26: niv: Xlx simprim library
38837: 02/01/26: niv: Re: Xlx simprim library
38845: 02/01/26: Rick Filipkiewicz: Re: Xlx simprim library
39445: 02/02/10: z.karim: Re: Xlx simprim library
38838: 02/01/26: Martin Fischer: Peaks in smaller PLDs
38839: 02/01/26: Falk Brunner: Re: Peaks in smaller PLDs
38906: 02/01/28: Martin Fischer: Re: Peaks in smaller PLDs
38927: 02/01/28: Falk Brunner: Re: Peaks in smaller PLDs
38930: 02/01/28: Peter Alfke: Re: Peaks in smaller PLDs
38946: 02/01/28: Falk Brunner: Re: Peaks in smaller PLDs
38951: 02/01/28: Peter Alfke: Re: Peaks in smaller PLDs
38843: 02/01/26: Paul: Altera support sites
38959: 02/01/28: Mike Treseler: Re: Altera support sites
39110: 02/01/31: Leon Heller: Re: Altera support sites
38853: 02/01/26: Mike Johnson: New Risc5x cpu core on Opencores
38867: 02/01/27: S. Ramirez: Re: New Risc5x cpu core on Opencores
38857: 02/01/26: Marcin E. Hamerla: Problem with Altera programmer
38858: 02/01/26: Tim: Re: Problem with Altera programmer
38913: 02/01/28: Iwo Mergler: Re: Problem with Altera programmer
38929: 02/01/28: Marcin E. Hamerla: Re: Problem with Altera programmer
38862: 02/01/27: Russell Shaw: Re: Problem with Altera programmer
38878: 02/01/27: Marcin E. Hamerla: Re: Problem with Altera programmer
38860: 02/01/26: Josh Pfrimmer: tri-state vs. Mux
38864: 02/01/27: Peter Alfke: Re: tri-state vs. Mux
38871: 02/01/27: rickman: Re: tri-state vs. Mux
38873: 02/01/26: Josh Pfrimmer: Re: tri-state vs. Mux
38868: 02/01/27: David Miller: Re: tri-state vs. Mux
38915: 02/01/28: Ray Andraka: Re: tri-state vs. Mux
38974: 02/01/29: Hal Murray: Re: tri-state vs. Mux
38984: 02/01/29: Jan Gray: Re: tri-state vs. Mux
38986: 02/01/29: Hal Murray: Re: tri-state vs. Mux
38875: 02/01/26: Sudip Saha: fpga device utilization
38879: 02/01/27: Falk Brunner: Re: fpga device utilization
38886: 02/01/27: Peter Alfke: Re: fpga device utilization
38890: 02/01/27: tollyska: 18bit counter
38892: 02/01/28: Muzaffer Kal: Re: 18bit counter
38991: 02/01/29: Davis Moore: Re: 18bit counter
39039: 02/01/30: Arash Salarian: Re: 18bit counter
38899: 02/01/27: Antonio: negative offset warning message
38907: 02/01/28: RS: Re: negative offset warning message
38922: 02/01/28: Antonio: Re: negative offset warning message
40267: 02/03/04: Edoardo: Re: negative offset warning message
38901: 02/01/27: Antonio: String manipulation in VHDL question
38902: 02/01/27: Antonio: Problem with type definition
38904: 02/01/28: Rob Finch: Is this a Xilinx XST synthesis problem ?
38905: 02/01/28: Przemyslaw Wegrzyn: Books on DSP
38923: 02/01/28: Tom: Re: Books on DSP
38933: 02/01/28: Ray Andraka: Re: Books on DSP
38937: 02/01/28: Tim: Re: Books on DSP
38987: 02/01/29: Tom Burgess: Re: Books on DSP
38988: 02/01/29: Ray Andraka: Re: Books on DSP
38996: 02/01/29: Tom Burgess: Re: Books on DSP
39035: 02/01/30: Ray Andraka: Re: Books on DSP
39010: 02/01/29: Kenny Huang: Re: Books on DSP
38908: 02/01/28: Arash Salarian: FPGA or Micro-controller in Lowpower designs?
38925: 02/01/28: rickman: Re: FPGA or Micro-controller in Lowpower designs?
38976: 02/01/29: Ulf Samuelsson: Re: FPGA or Micro-controller in Lowpower designs?
38982: 02/01/29: Arash Salarian: Re: FPGA or Micro-controller in Lowpower designs?
38983: 02/01/29: Arash Salarian: Re: FPGA or Micro-controller in Lowpower designs?
39008: 02/01/29: rickman: Re: FPGA or Micro-controller in Lowpower designs?
39026: 02/01/30: Hal Murray: Re: FPGA or Micro-controller in Lowpower designs?
39028: 02/01/30: Arash Salarian: Re: FPGA or Micro-controller in Lowpower designs?
39054: 02/01/31: Jim Granville: Re: FPGA or Micro-controller in Lowpower designs?
39096: 02/01/31: Ulf Samuelsson: Re: FPGA or Micro-controller in Lowpower designs?
39127: 02/02/01: rickman: Re: FPGA or Micro-controller in Lowpower designs?
39103: 02/01/31: Peter Alfke: Re: FPGA or Micro-controller in Lowpower designs?
39104: 02/01/31: Austin Lesea: Re: FPGA or Micro-controller in Lowpower designs?
39128: 02/02/01: rickman: Re: FPGA or Micro-controller in Lowpower designs?
39134: 02/02/01: Ulf Samuelsson: Re: FPGA or Micro-controller in Lowpower designs?
39178: 02/02/03: rickman: Re: FPGA or Micro-controller in Lowpower designs?
38955: 02/01/29: Jim Granville: Re: FPGA or Micro-controller in Lowpower designs?
39234: 02/02/04: Jay: Re: FPGA or Micro-controller in Lowpower designs?
39241: 02/02/05: Ray Andraka: Re: FPGA or Micro-controller in Lowpower designs?
39244: 02/02/05: Jim Granville: Re: FPGA or Micro-controller in Lowpower designs?
39248: 02/02/05: Ray Andraka: Re: FPGA or Micro-controller in Lowpower designs?
41059: 02/03/20: Matz: Re: FPGA or Micro-controller in Lowpower designs?
41066: 02/03/20: Peter Alfke: Re: FPGA or Micro-controller in Lowpower designs?
41069: 02/03/20: Tim: Re: FPGA or Micro-controller in Lowpower designs?
41079: 02/03/20: James Horn: Re: FPGA or Micro-controller in Lowpower designs?
41109: 02/03/21: Jim Granville: Re: FPGA or Micro-controller in Lowpower designs?
38911: 02/01/28: Steven Derrien: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38912: 02/01/28: Paul: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38914: 02/01/28: Steven Derrien: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38916: 02/01/28: Bill Blyth: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38917: 02/01/28: Steven Derrien: ARe: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38950: 02/01/28: Neil Glenn Jacobson: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39022: 02/01/30: Geert Van Doorselaer: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39027: 02/01/30: Steven Derrien: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39032: 02/01/30: Iwo Mergler: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39059: 02/01/30: Ray Andraka: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
39149: 02/02/01: Steen Larsen: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38920: 02/01/28: Antonio: Architectural question regarding ROM and RAM
38938: 02/01/28: Aare Tali: Spartan-2E data sheet (ds077_x.pdf)
38944: 02/01/28: Austin Lesea: Re: Spartan-2E data sheet (ds077_x.pdf)
38945: 02/01/28: Theron Hicks: glitchless clock enable/disable in spartanII
38956: 02/01/29: David Miller: Re: glitchless clock enable/disable in spartanII
38981: 02/01/29: Theron Hicks: Re: glitchless clock enable/disable in spartanII
38985: 02/01/29: Tim: Re: glitchless clock enable/disable in spartanII
39003: 02/01/29: Peter Alfke: Re: glitchless clock enable/disable in spartanII
39006: 02/01/30: Tim: Re: glitchless clock enable/disable in spartanII
38970: 02/01/29: Peter Alfke: Re: glitchless clock enable/disable in spartanII
38980: 02/01/29: Theron Hicks: Re: glitchless clock enable/disable in spartanII
39049: 02/01/30: Philip Freidin: Re: glitchless clock enable/disable in spartanII
39063: 02/01/30: Peter Alfke: Re: glitchless clock enable/disable in spartanII
39066: 02/01/30: Eric Smith: Re: glitchless clock enable/disable in spartanII
39067: 02/01/30: Peter Alfke: Re: glitchless clock enable/disable in spartanII
39073: 02/01/31: Rick Filipkiewicz: Re: glitchless clock enable/disable in spartanII
39101: 02/01/31: Peter Alfke: Re: glitchless clock enable/disable in spartanII
39076: 02/01/31: Philip Freidin: Re: glitchless clock enable/disable in spartanII
39119: 02/02/01: Rick Filipkiewicz: Re: glitchless clock enable/disable in spartanII
39120: 02/01/31: Peter Alfke: Re: glitchless clock enable/disable in spartanII
39121: 02/02/01: Philip Freidin: Re: glitchless clock enable/disable in spartanII
39157: 02/02/02: Rick Filipkiewicz: Re: glitchless clock enable/disable in spartanII
38948: 02/01/28: Tim: Spartan II power-up current - again
38953: 02/01/28: Austin Lesea: Re: Spartan II power-up current - again
39009: 02/01/29: rickman: Re: Spartan II power-up current - again
39034: 02/01/30: Austin Lesea: Re: Spartan II power-up current - again
39133: 02/02/01: Magnus Homann: Re: Spartan II power-up current - again
39043: 02/01/30: Deli Geng (David): Re: Spartan II power-up current - again
39050: 02/01/30: Austin Lesea: Re: Spartan II power-up current - again and again, and again, and .....
38949: 02/01/28: Jaap H. Mol: QuartusII Timing Analysis
38958: 02/01/29: Falk Brunner: The LUT puzzle, Iam on the way
38973: 02/01/29: Russell Shaw: Re: The LUT puzzle, Iam on the way
38994: 02/01/29: Falk Brunner: Re: The LUT puzzle, Iam on the way
39001: 02/01/30: Jim Granville: Re: The LUT puzzle, Iam on the way
39007: 02/01/29: Peter Alfke: Re: The LUT puzzle, Iam on the way
39030: 02/01/30: Ray Andraka: Re: The LUT puzzle, Iam on the way
39055: 02/01/30: Falk Brunner: Re: The LUT puzzle, Iam on the way
39058: 02/01/30: Ray Andraka: Re: The LUT puzzle, Iam on the way
39061: 02/01/30: Falk Brunner: Re: The LUT puzzle, Iam on the way
39065: 02/01/31: Jim Granville: Re: The LUT puzzle, Iam on the way
39064: 02/01/30: Peter Alfke: Re: The LUT puzzle, Iam on the way
39074: 02/01/31: Rick Filipkiewicz: Re: The LUT puzzle, Iam on the way
39089: 02/01/31: Ray Andraka: Re: The LUT puzzle, Iam on the way
39099: 02/01/31: Tim: Re: The LUT puzzle, Iam on the way
39140: 02/02/01: Ray Andraka: Re: The LUT puzzle, Iam on the way
39004: 02/01/30: Russell Shaw: Re: The LUT puzzle, Iam on the way
38979: 02/01/29: Jim Kearney: Re: The LUT puzzle, Iam on the way
38963: 02/01/29: Jim Granville: Soft errors climb in 0,13u SRAM
38989: 02/01/29: Michael Boehnel: Re: Soft errors climb in 0,13u SRAM
39002: 02/01/29: Austin Lesea: Re: Soft errors climb in 0,13u SRAM
38964: 02/01/28: piiszo: random
39017: 02/01/30: Srinivasan Venkataramanan: Re: random
39071: 02/01/30: piiszo: Re: random
39331: 02/02/06: Jay: Re: random
38969: 02/01/28: rickman: Boundary Scan Chain and JTAG Emulation of MSP430
38971: 02/01/28: Simon Hoffe: Importing ngo netlist into Foundation
38975: 02/01/29: Antonio: Memory Question on Virtex
38998: 02/01/29: Peter Alfke: Re: Memory Question on Virtex
39000: 02/01/29: Tom Burgess: Re: Memory Question on Virtex
39021: 02/01/30: Antonio: Re: Memory Question on Virtex
39048: 02/01/30: Tom Burgess: Re: Memory Question on Virtex
39075: 02/01/30: Antonio: Re: Memory Question on Virtex
39090: 02/01/31: Ray Andraka: Re: Memory Question on Virtex
38977: 02/01/29: Chris Cowdery: Flex10KA vs MAX7000S
38993: 02/01/29: Alan Nishioka: Re: Flex10KA vs MAX7000S
39014: 02/01/29: Kevin Brace: Re: Flex10KA vs MAX7000S
39037: 02/01/30: Chris Cowdery: Re: Flex10KA vs MAX7000S
39060: 02/01/30: Kevin Brace: Re: Flex10KA vs MAX7000S
39123: 02/02/01: rickman: Re: Flex10KA vs MAX7000S
39025: 02/01/30: Martin Thompson: Re: Flex10KA vs MAX7000S
39239: 02/02/04: Jay: Re: Flex10KA vs MAX7000S
38990: 02/01/29: Theron Hicks: dll error message in ModelSim XE/Starter 5.5b
38992: 02/01/29: Ray Andraka: Re: dll error message in ModelSim XE/Starter 5.5b
38995: 02/01/29: Falk Brunner: Dont care simulation
39033: 02/01/30: Ray Andraka: Re: Dont care simulation
38999: 02/01/29: Marceli Firlej: MapLab:30 Error in ISE 4.1i
39062: 02/01/30: Mark van de Belt: Re: MapLab:30 Error in ISE 4.1i
39005: 02/01/30: kryten_droid: Real-world keyboard signals
39023: 02/01/30: Falk: Re: Real-world keyboard signals
39012: 02/01/29: Sudip Saha: function synthesis.
39036: 02/01/30: Tim: Re: function synthesis.
39040: 02/01/30: Ray Andraka: Re: function synthesis.
39018: 02/01/29: Antonio: MUX with or without clk ??
39152: 02/02/02: <hamish@cloud.net.au>: Re: MUX with or without clk ??
39019: 02/01/29: Antonio: ROM dimension question
39068: 02/01/31: Tim: Re: ROM dimension question
39020: 02/01/29: Antonio: Signal assignment mismatch with Aldec 5.1 problem
39051: 02/01/30: Ray Andraka: Re: Signal assignment mismatch with Aldec 5.1 problem
39029: 02/01/30: newman: RLOCS with combinatorial logic
39057: 02/01/30: Ray Andraka: Re: RLOCS with combinatorial logic
39031: 02/01/30: Scott Thibault: Java or bytecode processors??
39041: 02/01/30: Hal Murray: Re: Java or bytecode processors??
39081: 02/01/31: Tim Sinkins: Re: Java or bytecode processors??
39088: 02/01/31: Scott Thibault: Re: Java or bytecode processors??
39079: 02/01/31: Jens Hildebrandt: Re: Java or bytecode processors??
39082: 02/01/31: Tauno Voipio: Re: Java or bytecode processors??
39044: 02/01/30: Hristo Stevic: 9 or 8 bits for image processing ?
39045: 02/01/30: Falk Brunner: Re: 9 or 8 bits for image processing ?
39047: 02/01/30: Ray Andraka: Re: 9 or 8 bits for image processing ?
39052: 02/01/30: Hristo Stevic: Re: 9 or 8 bits for image processing ?
39053: 02/01/30: Ray Andraka: Re: 9 or 8 bits for image processing ?
39072: 02/01/30: satya: JTAG Emulator Tutorial
39125: 02/02/01: rickman: Re: JTAG Emulator Tutorial
39077: 02/01/31: ssy: the cause of the simulation/synthesis mismatch
39117: 02/02/01: Rick Filipkiewicz: Re: the cause of the simulation/synthesis mismatch
39340: 02/02/06: Jay: Re: the cause of the simulation/synthesis mismatch
39405: 02/02/08: ssy: Re: the cause of the simulation/synthesis mismatch
39427: 02/02/08: Jay: Re: the cause of the simulation/synthesis mismatch
39078: 02/01/31: Marco Serafini: Setting PCI command register in WinNT OS
39107: 02/01/31: Eric Crabill: Re: Setting PCI command register in WinNT OS
39135: 02/02/01: Marco Serafini: Re: Setting PCI command register in WinNT OS
39145: 02/02/01: Eric Crabill: Re: Setting PCI command register in WinNT OS
39080: 02/01/31: Remco Poelstra: Xilinx XC3020-70
39094: 02/01/31: axel: Re: Xilinx XC3020-70
39095: 02/01/31: Remco Poelstra: Re: Xilinx XC3020-70
39097: 02/01/31: Philip Freidin: Re: Xilinx XC3020-70
39102: 02/01/31: Peter Alfke: Re: Xilinx XC3020-70
39083: 02/01/31: Goteb: ProcWizard by Gidel
39087: 02/01/31: Paul: Re: ProcWizard by Gidel
39084: 02/01/31: Gunther: WebPack 4.1 ISE Errors with Insight Demo files
39098: 02/01/31: Tim: Re: WebPack 4.1 ISE Errors with Insight Demo files
39115: 02/01/31: Arthur: Re: WebPack 4.1 ISE Errors with Insight Demo files
39086: 02/01/31: ssy: the post synthesis simulation problem
39092: 02/01/31: Austin Lesea: {72,64} extended hamming ECC
39100: 02/01/31: Tim: Re: {72,64} extended hamming ECC
39093: 02/01/31: Peter van Beek: meeting time critical conditions
39105: 02/01/31: Lasse Langwadt Christensen: skew between gated clks in Virtex2?
39108: 02/01/31: Peter Alfke: Re: skew between gated clks in Virtex2?
39109: 02/01/31: Austin Lesea: Re: skew between gated clks in Virtex2?
39293: 02/02/05: Lasse Langwadt Christensen: Re: skew between gated clks in Virtex2?
39106: 02/01/31: In Memory of tecNovia: Linking IP
39113: 02/01/31: Vikram: Re: Linking IP
39144: 02/02/01: Santiago de Pablo: Re: Linking IP
39147: 02/02/01: Ray Andraka: Re: Linking IP
39151: 02/02/02: <hamish@cloud.net.au>: Re: Linking IP
39158: 02/02/02: Allan Herriman: Re: Linking IP
39159: 02/02/02: Ray Andraka: Re: Linking IP
39111: 02/01/31: Maximilian Epple: metastability: failsafe solution???
39112: 02/01/31: Mike Treseler: Re: metastability: failsafe solution???
39137: 02/02/01: Maximilian Epple: Re: metastability: failsafe solution???
39114: 02/01/31: Igor Peker: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39124: 02/02/01: Kevin Brace: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39146: 02/02/01: Igor Peker: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39240: 02/02/05: sbf: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39270: 02/02/05: Mike Treseler: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39333: 02/02/06: Igor Peker: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39122: 02/01/31: rgf: www.easics.com
39142: 02/02/01: newman: Re: www.easics.com
39194: 02/02/03: rgf: Re: www.easics.com
39126: 02/01/31: MegaPoweSstar: JTAG Emulator Tutorial
39131: 02/01/31: strut911: Virtex2-3000 (XC2V3000) engineering samples and chipscope
39141: 02/02/01: Austin Lesea: Re: Virtex2-3000 (XC2V3000) engineering samples and chipscope
39377: 02/02/07: Jay: Re: Virtex2-3000 (XC2V3000) engineering samples and chipscope

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