16628: 99/06/01: <bdjmcw@sssdfdf.org>: THOUGHT YOU MIGHT LIKE THIS... 7902
16641: 99/06/01: Jarek Patrzalek: Fixed delay in FSM
16650: 99/06/01: Ray Andraka: Re: Fixed delay in FSM
16703: 99/06/03: Bill Gates: Re: Fixed delay in FSM
16651: 99/06/01: Victor Reyes: XILINX/ALTERA compatibility
16652: 99/06/01: Vitolo: XILINX/ALTERA compatibility
16699: 99/06/03: Bill Gates: Re: XILINX/ALTERA compatibility
16708: 99/06/03: David Hawke: Re: XILINX/ALTERA compatibility
16729: 99/06/04: Wenwei Qiao: Re: XILINX/ALTERA compatibility
16760: 99/06/07: David Hawke: Re: XILINX/ALTERA compatibility
16833: 99/06/11: Bill Gates: Re: XILINX/ALTERA compatibility
16756: 99/06/07: Neil Carrington: Re: XILINX/ALTERA compatibility
16656: 99/06/01: Eli Keren: CONTROLLED IMPEDANCE SOFTWARE
16659: 99/06/01: Michael T. Horne: New in the Qualis Library: BC case studies, design reuse, productivity scripts, info resources
16660: 99/06/01: <rajesh52@hotmail.com>: Verilog FAQ
16664: 99/06/01: Andrew Dauman: Synplicity Users Group Announcement
16665: 99/06/01: Michael T. Horne: Special Workshop on Design Reuse, June 16-17-18, San Jose, CA
16667: 99/06/01: news.pcnet.com: FPGA Introduction is needed, right?
16668: 99/06/01: Ray Andraka: Re: FPGA Introduction is needed, right?
16669: 99/06/02: <prastogi@my-deja.com>: Re: FPGA Introduction is needed, right?
16687: 99/06/02: Jonathan Feifarek: Re: FPGA Introduction is needed, right?
16721: 99/06/04: Michael Barr: Re: FPGA Introduction is needed, right?
16750: 99/06/06: news.pcnet.com: Re: FPGA Introduction is needed, right?
16697: 99/06/03: Bill Gates: Re: FPGA Introduction is needed, right?
16773: 99/06/08: Simon Armstrong: Re: FPGA Introduction is needed, right?
16677: 99/06/02: <micheal_thompson@my-deja.com>: FPGA/ VHDL books: any stores in central London
16695: 99/06/03: Rich Walker: Re: FPGA/ VHDL books: any stores in central London
16747: 99/06/06: Chris Eilbeck: Re: FPGA/ VHDL books: any stores in central London
16748: 99/06/06: Leon Heller: Re: FPGA/ VHDL books: any stores in central London
16689: 99/06/02: Richard D. Hunt: Rice Decompression Algorithm
16692: 99/06/03: Ties Bos: Q: How to set a "dont touch" attribute?
16693: 99/06/03: Nicolas Matringe: Altera EPC1 PROM + Data IO ChipWriter
16713: 99/06/03: Steve W.: Re: Altera EPC1 PROM + Data IO ChipWriter
16726: 99/06/04: Carlhermann Schlehaus: Re: Altera EPC1 PROM + Data IO ChipWriter
16757: 99/06/07: Victor Snesarev (EXCHANGE:BNRTP:3H18): Re: Altera EPC1 PROM + Data IO ChipWriter
16763: 99/06/07: Carlhermann Schlehaus: Re: Altera EPC1 PROM + Data IO ChipWriter
16786: 99/06/08: JA: Re: Altera EPC1 PROM + Data IO ChipWriter
16738: 99/06/04: Leonid Shvarzberg: Re: Altera EPC1 PROM + Data IO ChipWriter
16740: 99/06/05: Also-Antal Csaba: Red-Solomon enc/decoder
16694: 99/06/03: Steven K. Knapp: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
16701: 99/06/03: Bill Gates: Re: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
16698: 99/06/03: ds12: Using Virtex LUT and MULT_AND
16716: 99/06/04: Le mer Michel: Re: Using Virtex LUT and MULT_AND
16702: 99/06/03: Webmaster: Over 1450 Semiconductor Links!
16704: 99/06/03: Tom McLaughlin: Initial Values, Xilinx Virtex
16707: 99/06/03: Ray Andraka: Re: Initial Values, Xilinx Virtex
16719: 99/06/04: Tom McLaughlin: Re: Initial Values, Xilinx Virtex
16720: 99/06/04: Tom McLaughlin: Re: Initial Values, Xilinx Virtex
16735: 99/06/04: Hobson Frater: Re: Initial Values, Xilinx Virtex
16759: 99/06/07: Ray Andraka: Re: Initial Values, Xilinx Virtex
16787: 99/06/08: Hobson Frater: Re: Initial Values, Xilinx Virtex
16710: 99/06/03: Richard B. Katz: Registration is Open and Call for Papers - 1999 MAPLD International Conference
16714: 99/06/04: Erik de Castro Lopo: Xinx M1.5 under WinNT how to `nice' par
16717: 99/06/04: Lasse Langwadt Christensen: Re: Xinx M1.5 under WinNT how to `nice' par
16752: 99/06/07: Erik de Castro Lopo: Re: Xinx M1.5 under WinNT how to `nice' par
16754: 99/06/07: Lasse Langwadt Christensen: Re: Xinx M1.5 under WinNT how to `nice' par
16715: 99/06/04: Ha Young Youl: [Q] low cost asic
16742: 99/06/05: Alvin E. Toda: Re: [Q] low cost asic
16766: 99/06/07: Steven Casselman: Re: [Q] low cost asic
16764: 99/06/07: Jonathan Feifarek: Re: [Q] low cost asic
16722: 99/06/04: Jan Vermaete: Xilinx symbols, Viewlogic
16723: 99/06/04: Philip Freidin: Re: Xilinx symbols, Viewlogic
16724: 99/06/04: Austin Franklin: Re: Xilinx symbols, Viewlogic
16758: 99/06/07: Jan Vermaete: Re: Xilinx symbols, Viewlogic
16725: 99/06/04: Kyle Geske: Memec 8250 core with Xilinx Spartan device
16730: 99/06/04: David Tang: Re: Memec 8250 core with Xilinx Spartan device
16732: 99/06/04: Jonathan Bromley: Re: Memec 8250 core with Xilinx Spartan device
16743: 99/06/06: Rob Weinstein: Re: Memec 8250 core with Xilinx Spartan device
16745: 99/06/06: Jonathan Bromley: Re: Memec 8250 core with Xilinx Spartan device
16749: 99/06/06: Thierry Garrel: Re: Memec 8250 core with Xilinx Spartan device
16751: 99/06/06: Rickman: Re: Memec 8250 core with Xilinx Spartan device
16727: 99/06/04: Jonathan Bromley: Actel Desktop installation of Synplify won't work
16731: 99/06/04: Richard B. Katz: Re: Actel Desktop installation of Synplify won't work
16733: 99/06/04: Jonathan Bromley: Re: Actel Desktop installation of Synplify won't work
16737: 99/06/04: rk: Re: Actel Desktop installation of Synplify won't work
16785: 99/06/08: Jonathan Bromley: Re: Actel Desktop installation of Synplify won't work
16728: 99/06/04: Jeffrey L. Jensen: Re: The Chickenshit War in Kosovo!
16734: 99/06/04: Philip Freidin: Re: Xilinx symbols, Viewlogic
16739: 99/06/05: <rrhyxv@ffff.com>: FREE HARDCORE TEEN PICS 1683
16744: 99/06/06: <jcpsoft@my-deja.com>: Digital Filter Design Software
16755: 99/06/07: info: WaveFormer Pro & TestBencher Pro V6.0 Released
16761: 99/06/07: Anthony Ellis - LogicWorks: Any free timing diagram tools?
16775: 99/06/08: Steven K. Knapp: Re: Any free timing diagram tools?
16781: 99/06/08: George Cooper: Re: Any free timing diagram tools?
16762: 99/06/07: Frank Papendorf: FPGA interface SDRAM
16767: 99/06/07: Rickman: Re: FPGA interface SDRAM
16765: 99/06/07: John Heslip: Altera 10K I/O's
17196: 99/07/08: Jerry Zdenek: Re: Altera 10K I/O's
16768: 99/06/08: Allan Herriman: Q: Spartan XL pull-ups
16780: 99/06/08: Peter Alfke: Re: Q: Spartan XL pull-ups
16798: 99/06/09: Allan Herriman: Re: Q: Spartan XL pull-ups
16806: 99/06/09: Peter Alfke: Re: Q: Spartan XL pull-ups
16812: 99/06/10: Brian Boorman: Re: Q: Spartan XL pull-ups
16814: 99/06/10: Peter Alfke: Re: Q: Spartan XL pull-ups
16817: 99/06/11: Allan Herriman: Re: Q: Spartan XL pull-ups
16769: 99/06/07: Jason Lohn: Call for Participation: The First NASA/DoD Workshop on Evolvable
16770: 99/06/08: Stephen King: ALtera 20KE LVDS IO
16784: 99/06/08: Tom Burgess: Re: ALtera 20KE LVDS IO
16789: 99/06/08: muzo: Re: ALtera 20KE LVDS IO
16793: 99/06/08: Ying C.: Re: ALtera 20KE LVDS IO
16796: 99/06/09: Paulwb007: Re: ALtera 20KE LVDS IO
16799: 99/06/09: Stephen King: Re: ALtera 20KE LVDS IO
16772: 99/06/08: Rinux: mach210
16774: 99/06/08: Karim LIMAM: Sensitivity list assumed to be complete
16777: 99/06/08: Jonathan Bromley: Re: Sensitivity list assumed to be complete
16776: 99/06/08: khalid: LINE DELAYS USING RAMS
16779: 99/06/08: Jamie Sanderson: Re: LINE DELAYS USING RAMS
16782: 99/06/08: Peter Alfke: Re: LINE DELAYS USING RAMS
16783: 99/06/08: Tom Burgess: Re: LINE DELAYS USING RAMS
16788: 99/06/08: khalid: Re: LINE DELAYS USING RAMS
16792: 99/06/08: Peter Alfke: Re: LINE DELAYS USING RAMS
16795: 99/06/08: Ray Andraka: Re: LINE DELAYS USING RAMS
16797: 99/06/09: Lasse Langwadt Christensen: Re: LINE DELAYS USING RAMS
16802: 99/06/09: Ray Andraka: Re: LINE DELAYS USING RAMS
16807: 99/06/09: bob elkind: Re: LINE DELAYS USING RAMS
16808: 99/06/09: bob elkind: Re: LINE DELAYS USING RAMS
16778: 99/06/08: Artur Leung: FA: VHDL for Programmable Logic
16791: 99/06/08: Eugene Grayver: Die size of Xilinx FPGAs
16800: 99/06/09: Jonathan Bromley: Free IP library?????
16801: 99/06/09: Stephen Smith: Re: Free IP library?????
16846: 99/06/14: Reto Stamm: Re: Free IP library?????
16803: 99/06/09: Terry Fraser: Simultaneous switching outputs in Xilinx Spartan XL
16804: 99/06/09: Michael T. Horne: Last chance to register: Workshop on Design Reuse, June 16-17-18, San Jose, CA
16809: 99/06/09: Arrigo Benedetti: Looking for Xilinx Virtex devices
16810: 99/06/10: <mmobcl@hotmail.com>: Free Sex Links!! 9209
16811: 99/06/10: <ewngkj@hotmail.com>: Free Sex Links 7070
16813: 99/06/10: Thomas Rathgen: Configuring AlteraFlex10k with maxII
16818: 99/06/11: Markus Michel: Re: Configuring AlteraFlex10k with maxII
16859: 99/06/15: Steve W.: Re: Configuring AlteraFlex10k with maxII
16865: 99/06/15: Markus Michel: Re: Configuring AlteraFlex10k with maxII
16815: 99/06/11: david braendler: Virtex Boards
16829: 99/06/11: Tim Tyler: Re: Virtex Boards
16844: 99/06/14: Bill: Re: Virtex Boards
16834: 99/06/11: Steven K. Knapp: Re: Virtex Boards
16845: 99/06/14: Daryl Bradley: Re: Virtex Boards
16920: 99/06/16: John Schewel: Re: Virtex Boards
16925: 99/06/17: Daryl Bradley: Re: Virtex Boards
16926: 99/06/17: Kalle Palomäki: Re: Virtex Boards
16927: 99/06/17: Daryl Bradley: Re: Virtex Boards
16935: 99/06/17: Steven Casselman: Re: Virtex Boards
16940: 99/06/18: Daryl Bradley: Re: Virtex Boards
16942: 99/06/18: Bill: Re: Virtex Boards
16984: 99/06/22: Allan James Cantle: Availability of Parts
16965: 99/06/21: PaweƒE J. Rajda: Re: Virtex Boards
16979: 99/06/21: Steven Casselman: Re: Virtex Boards
16989: 99/06/22: Kalle Palomäki: Re: Virtex Boards
16816: 99/06/11: <nomad@vagabond.com>: test 6651
16819: 99/06/11: <gibsond@bournemouth.ac.uk>: Place & Route Xilinx F1.5 Student ed.
16820: 99/06/11: Reinoud: Re: Place & Route Xilinx F1.5 Student ed.
16822: 99/06/11: Brian Boorman: Re: Place & Route Xilinx F1.5 Student ed.
16827: 99/06/11: <gibsond@bournemouth.ac.uk>: Re: Place & Route Xilinx F1.5 Student ed.
16831: 99/06/11: Brian Boorman: Re: Place & Route Xilinx F1.5 Student ed.
16823: 99/06/11: <gibsond@bournemouth.ac.uk>: Re: Place & Route Xilinx F1.5 Student ed.
16824: 99/06/11: <gibsond@bournemouth.ac.uk>: Re: Place & Route Xilinx F1.5 Student ed.
16832: 99/06/11: Bill Gates: Re: Place & Route Xilinx F1.5 Student ed.
16842: 99/06/14: Reinoud: Re: Place & Route Xilinx F1.5 Student ed.
16828: 99/06/11: Philip Freidin: Re: Place & Route Xilinx F1.5 Student ed.
16850: 99/06/14: <gibsond@bournemouth.ac.uk>: Re: Place & Route Xilinx F1.5 Student ed.
16862: 99/06/15: <gibsond@bournemouth.ac.uk>: Re: Place & Route Xilinx F1.5 Student ed.
16821: 99/06/11: EDYNet Web Design & More: www.edy.net/jnonia
16825: 99/06/11: Davide Falchieri: FPGA Demonstration Board
16826: 99/06/11: Andy Bryant: PCI + I2O in a FPGA.... has anyone done it?
16835: 99/06/12: <austin@darkroom.com>: Re: PCI + I2O in a FPGA.... has anyone done it?
16851: 99/06/14: MTootell: Re: PCI + I2O in a FPGA.... has anyone done it?
16830: 99/06/11: christophe combaret: actel desktop
16836: 99/06/12: Juergen Otterbach: EPC2 and JTAG
16847: 99/06/14: Tino Konschak: Re: EPC2 and JTAG
16870: 99/06/15: Juergen Otterbach: Re: EPC2 and JTAG
155168: 13/05/22: <ece00380@myport.ac.uk>: Re: EPC2 and JTAG
16837: 99/06/12: =?iso-8859-1?Q?Jos=E9?= Antonio Moreno Zamora: Digital filters in VHDL
16838: 99/06/12: Ray Andraka: Re: Digital filters in VHDL
16839: 99/06/13: Hans: Re: Digital filters in VHDL
16856: 99/06/15: Leslie Yip (/ Loui): Re: Digital filters in VHDL/FPGA
16878: 99/06/15: Ray Andraka: Re: Digital filters in VHDL/FPGA
16881: 99/06/16: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Digital filters in VHDL
16840: 99/06/13: Simon Armstrong: comparative component pricing on www concept
16841: 99/06/14: Rajul Maheshwari: site for reconfigurable computing
16843: 99/06/14: Juan Antonio =?iso-8859-1?Q?G=F3mez?= Pulido: Float.p. with Xilinx Express VHDL
16848: 99/06/14: Adrian Donegan: Seen any good Boundary Scan companies?
16852: 99/06/14: Alain Cloet: Re: Seen any good Boundary Scan companies?
16896: 99/06/16: Adrian Donegan: Re: Seen any good Boundary Scan companies?
16849: 99/06/14: Qualicum Consulting: FAE In Ottawa ASAP!!!!!!! l-
16853: 99/06/14: Bill Balabanos: FPGA Express 3.00
16872: 99/06/15: Jim Kipps: Re: FPGA Express 3.00
16854: 99/06/14: Jonathan Bromley: Synplify problem - is it just me?
17143: 99/07/02: <ehiebert@my-deja.com>: Re: Synplify problem - is it just me?
17172: 99/07/07: <brian_m_davis@my-deja.com>: Re: Synplify problem - is it just me?
16855: 99/06/14: Ron: Problems programming Xilinx FPGAs
16871: 99/06/15: Peter Alfke: Re: Problems programming Xilinx FPGAs
16857: 99/06/15: Leslie Yip (/ Loui): delay line in FPGA / ASIC with VHDL
16858: 99/06/15: Leslie Yip (/ Loui): Re: delay line in FPGA / ASIC with VHDL
16874: 99/06/15: John Cooley: Re: delay line in FPGA / ASIC with VHDL
16877: 99/06/15: Ray Andraka: Re: delay line in FPGA / ASIC with VHDL
16897: 99/06/16: rk: Re: delay line in FPGA / ASIC with VHDL
16860: 99/06/15: Utku Ozcan: Xilinx DP RAM SPO Output
16886: 99/06/16: Le mer Michel: Re: Xilinx DP RAM SPO Output
16902: 99/06/16: Utku Ozcan: Re: Xilinx DP RAM SPO Output
16909: 99/06/16: Rickman: Re: Xilinx DP RAM SPO Output
16913: 99/06/16: Ray Andraka: Re: Xilinx DP RAM SPO Output
16962: 99/06/20: Sven Beyer: Re: Xilinx DP RAM SPO Output
17014: 99/06/24: Utku Ozcan: Re: Xilinx DP RAM SPO Output
16861: 99/06/15: Bernd Schmidt: Search for FPGA curcuits
16866: 99/06/15: Ruth Faulkner: Re: Search for FPGA curcuits
16863: 99/06/15: Alan Hall: Help with Foundation/Abel
16867: 99/06/15: Bertram Geiger: Re: Help with Foundation/Abel
16864: 99/06/15: Martin Maurer: 3 Questions with XILINX CPLD
16883: 99/06/16: Klaus Falser: Re: 3 Questions with XILINX CPLD
16885: 99/06/16: Le mer Michel: Re: 3 Questions with XILINX CPLD
16908: 99/06/16: Tom Burgess: Re: 3 Questions with XILINX CPLD
16868: 99/06/15: Davide Anguita: Which Virtex prototype board ?
16901: 99/06/16: Daryl Bradley: Re: Which Virtex prototype board ?
16869: 99/06/15: Garrick Kremesec: Altera EPC1 replacement?
16891: 99/06/16: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Altera EPC1 replacement?
16900: 99/06/16: Garrick Kremesec: Re: Altera EPC1 replacement?
17176: 99/07/07: Lior Dvir - Telrad LTD: Re: Altera EPC1 replacement?
16916: 99/06/17: Jason Pattison: Re: Altera EPC1 replacement?
16973: 99/06/22: lewis chen: Re: Altera EPC1 replacement?
17054: 99/06/28: Steven K. Knapp: Re: Altera EPC1 replacement?
17066: 99/06/28: Carlhermann Schlehaus: Re: Altera EPC1 replacement?
16873: 99/06/15: Default Profile: Make fast money!!!
16875: 99/06/15: vrml3d.com: newbie -- What's the best way to get started?
16876: 99/06/15: Ray Andraka: Re: newbie -- What's the best way to get started?
16892: 99/06/16: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: newbie -- What's the best way to get started?
16898: 99/06/16: rk: Re: newbie -- What's the best way to get started?
17046: 99/06/27: raravan: Re: newbie -- What's the best way to get started?
17052: 99/06/28: Steven K. Knapp: Re: newbie -- What's the best way to get started?
17133: 99/07/01: Barry Gershenfeld: Re: newbie -- What's the best way to get started?
17155: 99/07/05: Steven K. Knapp: Re: newbie -- What's the best way to get started?
16879: 99/06/16: Rickman: FPGA board for ISA bus wanted
16887: 99/06/16: Le mer Michel: Re: FPGA board for ISA bus wanted
16890: 99/06/16: wannarat: Re: FPGA board for ISA bus wanted
16889: 99/06/16: Ian St. John: Re: FPGA board for ISA bus wanted
16910: 99/06/16: Ray Andraka: Re: FPGA board for ISA bus wanted
16922: 99/06/17: Markus Wannemacher: Re: FPGA board for ISA bus wanted
16993: 99/06/22: APS: Re: FPGA board for ISA bus wanted
16880: 99/06/16: Sandro Wefel: Recursive Structures under Aldec AVHDL3.3
16903: 99/06/16: John McCluskey: Re: Recursive Structures under Aldec AVHDL3.3
16907: 99/06/16: Jaroslaw Kaczynski: Re: Recursive Structures under Aldec AVHDL3.3
16917: 99/06/16: John McCluskey: Re: Recursive Structures under Aldec AVHDL3.3
16919: 99/06/16: Ray Andraka: Re: Recursive Structures under Aldec AVHDL3.3
16911: 99/06/16: Ray Andraka: Re: Recursive Structures under Aldec AVHDL3.3
16882: 99/06/16: Anthony Ellis - LogicWorks: Altera/Synplicity TIMESTAMP?
16893: 99/06/16: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Altera/Synplicity TIMESTAMP?
16899: 99/06/16: Anthony Ellis - LogicWorks: Re: Altera/Synplicity TIMESTAMP?
16994: 99/06/22: Jeff Kiser: Re: Altera/Synplicity TIMESTAMP?
16884: 99/06/16: Michael Gillies: Timing Benchmark for FPGA based DSP
16888: 99/06/16: wannarat: aobut analog
16906: 99/06/16: Andy Peters: Re: aobut analog
16914: 99/06/16: Ray Andraka: Re: aobut analog
16921: 99/06/17: Sandro Wefel: Re: aobut analog
16932: 99/06/17: Tom Burgess: Re: aobut analog
16934: 99/06/17: Steven Casselman: Re: aobut analog
16894: 99/06/16: IPU: vhdl and viewlogic problem
16905: 99/06/16: Andy Peters: Re: vhdl and viewlogic problem
16915: 99/06/16: Ray Andraka: Re: vhdl and viewlogic problem
16895: 99/06/16: Ingo Purnhagen: vhdl and viewlogic problem
16941: 99/06/18: Jim Kipps: Re: vhdl and viewlogic problem
16943: 99/06/18: Austin Franklin: Re: vhdl and viewlogic problem
16953: 99/06/18: Ray Andraka: Re: vhdl and viewlogic problem
16912: 99/06/16: <nikos@bops.com>: JOB: Employment Opportunities at BOPS (Chapel Hill, NC)
16924: 99/06/17: Eugene Grayver: Die size of XILINX fpga's
16939: 99/06/18: Dave Storrar: Re: Die size of XILINX fpga's
16929: 99/06/17: Joshua Lamorie: Logic factoring program
16930: 99/06/17: <sw>: DS2 and E2 Framer???
17001: 99/06/23: Gerry Schneider: Re: DS2 and E2 Framer???
17031: 99/06/25: Steve W.: Re: DS2 and E2 Framer???
16931: 99/06/17: Sung H. Lim: Actel ActGen and Desktop problem
16938: 99/06/18: zootsuit: Re: Actel ActGen and Desktop problem
16933: 99/06/17: Martin Duffy: Actel's proASIC
16963: 99/06/21: Richard Guerin: Re: Actel's proASIC
16936: 99/06/18: bob: *.bit, *.ubt, *.rbt
16937: 99/06/17: Wade D. Peterson: WISHBONE Interconnection Standard for IP Core Reuse
16944: 99/06/18: Thomas A. Coonan: Read/Writes to memories/register files for PIC core
16945: 99/06/18: Rickman: Re: Read/Writes to memories/register files for PIC core
16948: 99/06/18: Thomas A. Coonan: Re: Read/Writes to memories/register files for PIC core
16952: 99/06/18: Jan Gray: Re: Read/Writes to memories/register files for PIC core
16955: 99/06/19: <ems@riverside-machines.com.NOSPAM>: Re: Read/Writes to memories/register files for PIC core
16964: 99/06/21: Jan Gray: Re: Read/Writes to memories/register files for PIC core
17004: 99/06/23: <ems@riverside-machines.com.NOSPAM>: Re: Read/Writes to memories/register files for PIC core
16946: 99/06/18: Andy Peters: Re: Read/Writes to memories/register files for PIC core
16949: 99/06/18: Wade D. Peterson: Re: Read/Writes to memories/register files for PIC core
16951: 99/06/18: Wade D. Peterson: Re: Read/Writes to memories/register files for PIC core
16960: 99/06/19: Thomas A. Coonan: Re: Read/Writes to memories/register files for PIC core
17020: 99/06/25: Paul Walker: Re: Read/Writes to memories/register files for PIC core
17024: 99/06/25: Stephen Swearingen: Re: Read/Writes to memories/register files for PIC core
17044: 99/06/28: Thomas A. Coonan: Re: Read/Writes to memories/register files for PIC core
17045: 99/06/27: Rickman: Re: Read/Writes to memories/register files for PIC core
17048: 99/06/28: Braam: Re: Read/Writes to memories/register files for PIC core
17057: 99/06/28: Andy Peters: Re: Read/Writes to memories/register files for PIC core
17069: 99/06/28: Thomas A. Coonan: Re: Read/Writes to memories/register files for PIC core
17071: 99/06/29: Ray Andraka: Re: Read/Writes to memories/register files for PIC core
17078: 99/06/29: Jamie Lokier: Re: Read/Writes to memories/register files for PIC core
17080: 99/06/29: Ray Andraka: Re: Read/Writes to memories/register files for PIC core
17094: 99/06/30: Jamie Lokier: Re: Read/Writes to memories/register files for PIC core
17073: 99/06/29: Rickman: Re: Read/Writes to memories/register files for PIC core
17075: 99/06/29: Peter Alfke: Re: Read/Writes to memories/register files for PIC core
17077: 99/06/29: Ulf Samuelsson: Re: Read/Writes to memories/register files for PIC core
17081: 99/06/29: Ray Andraka: Re: Read/Writes to memories/register files for PIC core
17086: 99/06/29: Thomas A. Coonan: Re: Read/Writes to memories/register files for PIC core
17093: 99/06/29: Rickman: Re: Read/Writes to memories/register files for PIC core
16947: 99/06/18: Brian Boorman: FW: Xilinx Acquisition of CoolRunners
16950: 99/06/18: Tom Burgess: Re: FW: Xilinx Acquisition of CoolRunners
17084: 99/06/29: Steven J. Ackerman: Re: FW: Xilinx Acquisition of CoolRunners
17105: 99/06/30: Peter Alfke: Re: FW: Xilinx Acquisition of CoolRunners
17112: 99/07/01: WildBeach: Re: FW: Xilinx Acquisition of CoolRunners
17124: 99/07/01: Peter Alfke: Re: FW: Xilinx Acquisition of CoolRunners
17126: 99/07/01: Ray Andraka: Re: FW: Xilinx Acquisition of CoolRunners
17141: 99/07/02: Peter Alfke: Re: FW: Xilinx Acquisition of CoolRunners
17150: 99/07/03: Stuart Clubb: Re: FW: Xilinx Acquisition of CoolRunners
17130: 99/07/01: Mark Aaldering: Re: FW: Xilinx Acquisition of CoolRunners
17149: 99/07/04: jim granville: Re: FW: Xilinx Acquisition of CoolRunners
17218: 99/07/09: Peter: Re: FW: Xilinx Acquisition of CoolRunners
17139: 99/07/02: Steven Casselman: Re: FW: Xilinx Acquisition of CoolRunners
17140: 99/07/02: Richard Dungan: Re: FW: Xilinx Acquisition of CoolRunners
16954: 99/06/18: Steven Casselman: Re: Simple PCI card prototyping.
16956: 99/06/19: Brian Drummond: Re: Simple PCI card prototyping.
16972: 99/06/21: Austin Franklin: Re: Simple PCI card prototyping.
16985: 99/06/22: Brian Drummond: Re: Simple PCI card prototyping.
16986: 99/06/22: Austin Franklin: Re: Simple PCI card prototyping.
16991: 99/06/22: Steven Casselman: Re: Simple PCI card prototyping.
17006: 99/06/23: Brian Drummond: Re: Simple PCI card prototyping.
17008: 99/06/23: Austin Franklin: Re: Simple PCI card prototyping.
17067: 99/06/28: Steven Casselman: Re: Simple PCI card prototyping.
17151: 99/07/04: Austin Franklin: Re: Simple PCI card prototyping.
17168: 99/07/06: Steven Casselman: Re: Simple PCI card prototyping.
17193: 99/07/08: Austin Franklin: Re: Simple PCI card prototyping.
16995: 99/06/22: APS: Re: Simple PCI card prototyping.
16957: 99/06/19: Tibor Szolnoki: Synopsys FPGA Express vs. Compiler II
17012: 99/06/24: Jim Kipps: Re: Synopsys FPGA Express vs. Compiler II
17032: 99/06/26: <ems@riverside-machines.com.NOSPAM>: Re: Synopsys FPGA Express vs. Compiler II
16958: 99/06/19: Tibor Szolnoki: Re: Synopsys FPGA Express vs. Compiler II
16959: 99/06/19: EKC: Vendor Market Share
16961: 99/06/20: Alan Hall: More help with Foundation
17098: 99/06/30: Matthias Fuchs: Re: More help with Foundation
16966: 99/06/21: DEEPAK KUMAR T: PLL for FPGA
16970: 99/06/21: Anurag: Re: PLL for FPGA
16996: 99/06/22: APS: Re: PLL for FPGA
16967: 99/06/21: jgjhg ghjg: XILINX PROG-PIN unconnected?
16968: 99/06/21: woellik helmut: XILINX PROG-PIN unconnected?
16969: 99/06/21: Graham Eastwood: Viewdraw + Foundation Express design flow
17011: 99/06/24: Jim Kipps: Re: Viewdraw + Foundation Express design flow
16971: 99/06/21: Anurag: FPGA in Wireless Designs
16975: 99/06/21: Philip Freidin: Re: FPGA in Wireless Designs
16978: 99/06/21: Jonathan Feifarek: Re: FPGA in Wireless Designs
17002: 99/06/22: Richard Schwarz: Re: FPGA in Wireless Designs
16974: 99/06/21: <rtumkur7009@my-deja.com>: Design using OrCAD 7.2
16976: 99/06/21: Steve Charlwood: Question: Does FPGA Express 3.2 support RPMs?
16982: 99/06/22: Jan Gray: Re: Question: Does FPGA Express 3.2 support RPMs?
16977: 99/06/21: Steve Charlwood: Request for information on discontinued Xilinx XC4000-series variants
16981: 99/06/21: Peter Alfke: Re: Request for information on discontinued Xilinx XC4000-series
17015: 99/06/24: Philip Freidin: Re: Request for information on discontinued Xilinx XC4000-series variants
17039: 99/06/27: Peter: Re: Request for information on discontinued Xilinx XC4000-series variants
17043: 99/06/27: Philip Freidin: Re: Request for information on discontinued Xilinx XC4000-series variants
17051: 99/06/28: Peter Alfke: Re: Request for information on discontinued Xilinx XC4000-series
16980: 99/06/21: <kfrod@my-deja.com>: pdf files
16983: 99/06/22: Jan Gray: Xilinx "Virtex Configuration Architecture Advanced Users' Guide" appears
17005: 99/06/23: tom meany: Purchase of Spartan chips on the internet
17009: 99/06/23: Ray Andraka: Re: Purchase of Spartan chips on the internet
16987: 99/06/22: <vermon1055@my-deja.com>: Synopsys DC & FPGA Compiler
17013: 99/06/24: Jim Kipps: Re: Synopsys DC & FPGA Compiler
16988: 99/06/22: AK: ProASIC
16990: 99/06/22: Bernd Schmidt: FPGA benchmarks
17016: 99/06/24: Brian Dipert: Re: FPGA benchmarks
16998: 99/06/22: SIGTEK: QPSK Constellation Permutations Article in SIGTEK SOftware Radio
17000: 99/06/22: John Janusson: Re: Exhaustedly I come for Digital PLL help
17090: 99/06/29: jok: Re: Exhaustedly I come for Digital PLL help
17007: 99/06/23: Tom Liehe: Virtex data sheet is incomplete
17022: 99/06/25: Tom Liehe: Re: Virtex data sheet is incomplete
17023: 99/06/25: Rickman: Re: Virtex data sheet is incomplete
17033: 99/06/26: <ems@riverside-machines.com.NOSPAM>: Re: Virtex data sheet is incomplete
17010: 99/06/23: <owlcdg@thankyou.com>: Disney vacation 1006
17017: 99/06/24: <sheilasu@my-deja.com>: please advise on standard cell libraries
17018: 99/06/24: <sheilasu@my-deja.com>: please advise on standard cell libraries
17019: 99/06/25: <lnarayan@hclt.com>: synopsys message "unable to resolve reference" with 4000xv
17021: 99/06/25: Ray Andraka: www.reconfig.com
17025: 99/06/25: Robert K. Veazey Jr.: 100 Billion operations per sec.!
17026: 99/06/25: Jonathan Feifarek: Re: 100 Billion operations per sec.!
17053: 99/06/28: Don HUsby: Re: 100 Billion operations per sec.!
17058: 99/06/28: glen herrmannsfeldt: Re: 100 Billion operations per sec.!
17064: 99/06/28: Don HUsby: Re: 100 Billion operations per sec.!
17059: 99/06/28: Steven Casselman: Re: 100 Billion operations per sec.!
17072: 99/06/29: Tom Kean: Re: 100 Billion operations per sec.!
17083: 99/06/29: Steven Casselman: Re: 100 Billion operations per sec.!
17089: 99/06/30: Tom Kean: Re: 100 Billion operations per sec.!
17142: 99/07/02: Steven Casselman: Re: 100 Billion operations per sec.!
17145: 99/07/03: Tom Kean: Re: 100 Billion operations per sec.!
17171: 99/07/06: Steven Casselman: Re: 100 Billion operations per sec.!
17192: 99/07/08: Austin Franklin: Re: 100 Billion operations per sec.!
17202: 99/07/08: Tom Kean: Re: 100 Billion operations per sec.!
17232: 99/07/12: Mike Butts: Re: 100 Billion operations per sec.!
17239: 99/07/13: Steven Casselman: Re: 100 Billion operations per sec.!
17063: 99/06/28: Austin Franklin: Re: 100 Billion operations per sec.!
17030: 99/06/25: Ray Andraka: Re: 100 Billion operations per sec.!
17041: 99/06/27: Robert K. Veazey Jr.: Re: 100 Billion operations per sec.!
17179: 99/07/07: Mark Grindell: Re: 100 Billion operations per sec.!
17180: 99/07/07: Mark Grindell: Re: 100 Billion operations per sec.!
17190: 99/07/07: Ray Andraka: Re: 100 Billion operations per sec.!
17203: 99/07/08: Brad L. Hutchings: Re: 100 Billion operations per sec.!
17027: 99/06/26: Lars FREUND: Altera: Simulation results differ...
17042: 99/06/27: Henning Trispel: Re: Altera: Simulation results differ...
17028: 99/06/25: Andy Peters: fast counter in 4013XL?
17029: 99/06/25: Ray Andraka: Re: fast counter in 4013XL?
17034: 99/06/26: Stuart Clubb: Re: fast counter in 4013XL?
17038: 99/06/26: Rickman: Re: fast counter in 4013XL?
17056: 99/06/28: Andy Peters: Re: fast counter in 4013XL?
17055: 99/06/28: Andy Peters: Re: fast counter in 4013XL?
17040: 99/06/27: Yip: Re: fast counter in 4013XL?
17068: 99/06/28: Andy Peters: Re: pessimistic synth results (was: fast counter in 4013XL?)
17103: 99/06/30: Aurel Wosylus: Re: fast counter in 4013XL?
17106: 99/06/30: Andy Peters: Re: fast counter in 4013XL?
17035: 99/06/26: <adamjone@purdue.edu>: Virtex JTAG readback
17049: 99/06/28: Albano, David (EXCHANGE:RTP:3H91): Re: Virtex JTAG readback
17099: 99/06/30: Bill: Re: Virtex JTAG readback
17092: 99/06/29: Alvin E. Toda: Re: Virtex JTAG readback
17111: 99/07/01: <adamjone@purdue.edu>: Re: Virtex JTAG readback
17129: 99/07/01: bob elkind: Altera, JTAG, and FPGAs WAS: Virtex JTAG readback
17036: 99/06/26: Edward Moore: Major Exemplar Bug
17037: 99/06/26: Michelle Tran: IP Cores for FPGA
17047: 99/06/28: Nico L.: .shp, .shx, .dbf file conversion. help !
17050: 99/06/28: <channing@my-deja.com>: How to build a NetBridge use FPGA
17115: 99/07/01: Mark Woods: Re: How to build a NetBridge use FPGA
17060: 99/06/28: <oipugliufed@8uihsdrfsa.com>: Adults Only! 46829
17061: 99/06/28: <outo@Wfsdfsdf.com>: Fresh Young 53427
17062: 99/06/28: Asher C. Martin: ALTERA GDF to VHDL QUESTION
17123: 99/07/01: Jaya Rajesh: Re: ALTERA GDF to VHDL QUESTION
17125: 99/07/01: Rickman: Re: ALTERA GDF to VHDL QUESTION
17132: 99/07/01: <mench@mench.com>: Re: OrCAD (was "Re: ALTERA GDF to VHDL QUESTION")
17138: 99/07/02: Jaya Rajesh: Re: ALTERA GDF to VHDL QUESTION
17178: 99/07/07: Mark Grindell: Re: ALTERA GDF to VHDL QUESTION
17065: 99/06/28: EKC: FGPA Servo Motor Controller
17082: 99/06/29: Brian Philofsky: Re: FGPA Servo Motor Controller
17087: 99/06/30: Joseph H Allen: Re: FGPA Servo Motor Controller
17088: 99/06/29: Ray Andraka: Re: FGPA Servo Motor Controller
17135: 99/07/02: Steven J. Ackerman: Re: FGPA Servo Motor Controller
17136: 99/07/02: Joseph H Allen: Re: FGPA Servo Motor Controller
17134: 99/07/01: <tryggvem@my-deja.com>: Re: FGPA Servo Motor Controller
17070: 99/06/29: <ginger987@aol.com>: 18+ 62321
17074: 99/06/29: Sven =?iso-8859-1?Q?L=FCcke?=: altera flex 10k20 dedicated input
17076: 99/06/29: Chris Squires: Re: altera flex 10k20 dedicated input
17079: 99/06/29: <micheal_thompson@my-deja.com>: Altera SDF file missing some DFF VITAL generics?
17085: 99/06/29: GOVJOBS.COM: FPGA - Ground Unit Design Engineering
17091: 99/06/29: Rickman: uLaw and ALaw conversion in an FPGA
17097: 99/06/30: Allan Herriman: Re: uLaw and ALaw conversion in an FPGA
17104: 99/06/30: Pawel Michocki: Re: uLaw and ALaw conversion in an FPGA
17108: 99/06/30: Lasse Langwadt Christensen: Re: uLaw and ALaw conversion in an FPGA
17110: 99/06/30: Ray Andraka: Re: uLaw and ALaw conversion in an FPGA
17113: 99/07/01: Rickman: Re: uLaw and ALaw conversion in an FPGA
17120: 99/07/01: Lasse Langwadt Christensen: Re: uLaw and ALaw conversion in an FPGA
17095: 99/06/30: Rickman: Re: uLaw and ALaw conversion in an FPGA
17096: 99/06/30: ischoi(etri.re.kr): Q: About input/output_delay constraints in Synopsys Design compiler
17100: 99/06/30: Matthias Fuchs: xilinx Foundation map-warning
17101: 99/06/30: Matthias Fuchs: foundation F1.5i warning:
17102: 99/06/30: Jorge Guajardo: Accepted Papers at CHES

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