Showing posts with label engineering. Show all posts
Showing posts with label engineering. Show all posts

Tuesday, June 9, 2015

How to make an FPGA Partially Reconfigurable

Partially reconfiguration means changing the FPGA partially or only the selected part of the FPGA is reconfigured. It can be done in two ways:

i) Module based partial reconfiguration
Partial reconfiguration on the basis of difference

Module based partial reconfiguration:


In module based reconfiguration we reconfigure on the specific module or only by changing a selected module we can do the partially reconfiguration of our FPGA. The portions of the design to be reconfigured are known as reconfigurable modules. Specific properties and specific layout criteria must be met with respect to a reconfigurable module, FPGA design intending to use partial reconfiguration must be planned and laid out with that in mind.

Partial reconfiguration on the basis of difference:


Partial reconfiguration on the basis of difference is a method of making small changes in an FPGA design, such as changing I/O standards, LUT equations, and block RAM content.

Applications:


i) To lessen power or making the design power-efficient.
ii) Through the JTRS Program, SDRs are becoming a reality for the defense industries as an effective and necessary tool for communication. SDRs assure the JTRS standard by having both a software-reprogrammable operating environment and the ability to support multiple channels and networks simultaneously.
iii) Partial reconfiguration is useful in a variety of applications across many industries. The aerospace and defense industries have certainly taken advantage of its capabilities.
iv) Increased system performance. Although a portion of the design is being reconfigured, the rest of the system can keep on to operate. There is no loss of performance or functionality with unaffected portions of a design.
v) Hardware sharing. Because partial reconfiguration allows you to run multiple applications on a single FPGA, hardware sharing is realized. Benefits include reduced device count, reduced power consumption, smaller boards, and in particular lower costs.

key steps used in Xilinx to make the FPGA partially Reconfigured:


1: First Create Processor Hardware System.
2: Then Create Software Project.
3: After then Create a Plan ahead Project.
4: Defining a Reconfigurable Partition.
5: Adding Reconfigurable Modules.
6: significant the Reconfigurable Partition Region.
7: Running the Design Rule Checker.
8: Then Create the First Configuration, Implementing, and Promoting.
9: Then Create Other Configurations, and Implementing.
10: Then Run Partial Reconfiguration to Verify Utility.
11: Generating Bit Files.
12: Creating an Image, and Testing.

Advantages:


There are many advantages to make the FPGA reconfigured. only some from them are following:

I) To make the device more efficient.
II) To lessen the LUTs of the design by replacing only specific portion.
III) To lessen power of the design by replacing only specific portion.
IV) To lessen the delay of the design by replacing only specific portion or a specific module.





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Tuesday, May 19, 2015

Surround View System for Vehicles and its Advantages for Drivers



ADAS - Advanced Driving Assistance System is a very popular research area all around the globe and has unbelievable future scope. Within ADAS, the latest developing area and market is of Surround view system or Surround vision or Top view system. These systems are meant to provide a central display of the vehicle to the driver from the perspective of a bird's vision. Hence, another name given to such systems is "Birds' eye view". A glimpse of Surround vision is shown in the figure below. As the name suggests, surround view system provides the view of immediate surroundings to the drivers. Such views are of great assistance to the drivers in precise operations viz., parking maneuvers, driving in heavy traffic conditions etc.




Any bird eye vision system typically involves 4-6 wide angle fish-eye lens cameras mounted all around the vehicle. The installed/mounted cameras have Field of View up to 180 degrees. Such lenses are preferred so that immediate surrounding is completely visible even after the data loss during the implementation of algorithm on captured frames.

Two types of camera arrangements are generally seen:

  • 4 cameras: front, back and one on each side view mirrors.
  • 6 cameras: 1 on all four corners, front and back.
Out of these two, the former is most common because of reasons like lesser complications, initial cost-effectiveness etc.

Advantages to Drivers:
  1. Assistance in parking maneuvers because surrounding vehicles and parking slots are easily visible and driver can solely focus on driving rather than peeping into the mirrors for parking safely.
  2. Eliminates the use of mirrors by providing the complete view of surrounding on a single screen.
  3. Any object or vehicle approaching or running close to the vehicle is visible at once.
  4. Being "top-view", the system is free of perspective distortion. In layman's language, drivers are free of constraints like "Objects in the mirror are closer than they appear".
  5. Works properly even on slopes because of reasonably large field of view.
  6. Driver error is reduced or even eliminated, and efficiency in traffic and transport is enhanced.
  7. High-performance driving can be conducted regardless of the vision, weather and environmental conditions.
  8. Many more vehicles can be accommodated, on regular highways but especially on dedicated lanes

Monday, April 20, 2015

Low Power Techniques in the FINFET



Fin type field effect transistors (FINFETs) is a new type of CMOS in VLSI . These are doubled gated device. The two gates of a FINFET can either be shorted or independently controlled for lower leakage. It has lower short channel effects (SCEs) and ideal sub threshold voltage. To make a FINFET, the front oxide is made much thicker than the side oxides in order to effectively deactivate the front gate. We call this device FINFET because the thin channel region stands vertically similar to the fin between the sources and drain regions.

There are different modes of FINFET (a) Short gate (SG) mode (b) Independent gate (IG) mode (c) Low power (LP) mode (d) A hybrid IG/LP-mode.

  1. SG Mode:In this mode both gate are shorted and we get good control over the channel length
  2. IG Mode:In this independent signals are provided to the two device gates, this will reduce the number of transistors in the circuit.
  3. LP mode:In this we are applying a low voltage to n type FINFET and high voltage to P type FINFET.
  4. Hybrid mode:It is a combination of LP and IG modes.
Different techniques for low power consumption:

a)DTCMOS:This technique reduces standby power by using the P-MOS switch with higher threshold voltage in between power supply and the circuit. It can also use N-MOS switches with higher threshold voltage in between ground and the circuit. This high threshold transistors can operate with high speed and low switching power dissipation. When the circuit is in OFF mode the high threshold transistors are turned OFF causing reduction in the sub-threshold leakage current.

b)Self Controlled Voltage Level(SVL): There are three types of SVL techniques:

  • Type-1 has an upper SVL circuit, in this we can use single P-MOS switch and n no. of N-MOS switches connected in series. The ON P-MOS connects a power supply and the load circuit in the active mode and the all N-MOS are disconnected and they are in standby mode.
  • Type-2 has a lower SVL circuit, in which we use single N-MOS switch and n no. of P-MOS switches connected in series. The lower SVL circuit not only supplies 0 to the active-load circuit through the ON N-MOS but also supplies 0 to the standby load circuit through the use of the ON P-MOS.
  • Type-3 has a combination of lower and upper SVL circuit.When the gate voltage of circuit is kept at 0, the P-MOS is turned ON while the N-MOS is turned OFF. The current is pass through the P-MOS and through the n P-MOS in the lower circuit. When control signal turns to 1 the N-MOS is turned ON and turns OFF P-MOS, power is supplied to the circuit through n N-MOS. This results in a decrease in the sub threshold current of the N-MOS that is the leakage current through the circuit decreases.

Friday, April 17, 2015

Hardware Co-simulation for Non Memory Mapped Ports using Simulink and System Generator



Hardware or FPGA is a primary requirement for any real time implementation of mathematical algorithms. The main drawback of the process is the limited resources and the interfaces available on the FPGA for the co-simulation process. One of the main highlighted concern is the mapping of the peripheral ports on the FPGA with the algorithm.

Co-simulation is the best process to use for the real time implementation of the algorithms because the process facilitates the features of the two tools simultaneously. MATLAB is known as the best tool for the implementation of the mathematical algorithms for a number of applications. The other tool System Generator from by the Xilinx is known best for the hardware implementation of the algorithms.

Both the tools work together simultaneously to real time implementation of the mathematical algorithms on the FPGAs. The complications are their when you want to use the LEDs, Buttons or other output devices. To resolve these problems we manually create the Non Memory Mapped Ports according to the steps given below.

To manually create NMM we need these different Simulink and system generator block sets.
1.In1
2.Convert
3.Gateway In
4.Out1
5.Terminator

To generate the library subsystem we have to put these block as in the given fig:1

Fig: 1

The work is almost done we just need to run the given three command on the MATLAB command window after selecting the “Gateway Out” block

>>xlSetNonMemMap(gcbh, 'Xilinx', 'ethernetcosim');
>>xlSetPortParams(gcbh, 'IOConstraint', 'NET "pmod0" LOC = U18;');

This command is to map output of the design to the LED of the FPGA . “U18” is the pin location of the LED<0> in our case and can be changed on the basis of different pin location of the FPGAs.

>>dump(xlGetPortParams(gcbh));

This command is to confirm the pin mapping.

To use these blocks, right click after selecting all the blocks and make subsystem of them and put the subsystem wherever you want to use with any Simulink model.


The block is now ready to use for the NMM.
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