Showing posts with label MATLAB. Show all posts
Showing posts with label MATLAB. Show all posts

Friday, April 17, 2015

Hardware Co-simulation for Non Memory Mapped Ports using Simulink and System Generator



Hardware or FPGA is a primary requirement for any real time implementation of mathematical algorithms. The main drawback of the process is the limited resources and the interfaces available on the FPGA for the co-simulation process. One of the main highlighted concern is the mapping of the peripheral ports on the FPGA with the algorithm.

Co-simulation is the best process to use for the real time implementation of the algorithms because the process facilitates the features of the two tools simultaneously. MATLAB is known as the best tool for the implementation of the mathematical algorithms for a number of applications. The other tool System Generator from by the Xilinx is known best for the hardware implementation of the algorithms.

Both the tools work together simultaneously to real time implementation of the mathematical algorithms on the FPGAs. The complications are their when you want to use the LEDs, Buttons or other output devices. To resolve these problems we manually create the Non Memory Mapped Ports according to the steps given below.

To manually create NMM we need these different Simulink and system generator block sets.
1.In1
2.Convert
3.Gateway In
4.Out1
5.Terminator

To generate the library subsystem we have to put these block as in the given fig:1

Fig: 1

The work is almost done we just need to run the given three command on the MATLAB command window after selecting the “Gateway Out” block

>>xlSetNonMemMap(gcbh, 'Xilinx', 'ethernetcosim');
>>xlSetPortParams(gcbh, 'IOConstraint', 'NET "pmod0" LOC = U18;');

This command is to map output of the design to the LED of the FPGA . “U18” is the pin location of the LED<0> in our case and can be changed on the basis of different pin location of the FPGAs.

>>dump(xlGetPortParams(gcbh));

This command is to confirm the pin mapping.

To use these blocks, right click after selecting all the blocks and make subsystem of them and put the subsystem wherever you want to use with any Simulink model.


The block is now ready to use for the NMM.

Wednesday, August 20, 2014

How to start with System Generator

System generator is the high level tool designed especially for high performance DSP systems using all Xilinx programmable devices. System generator for DSP provide high quality DSP algorithm which accelerate the development in less time as compared to traditional RTL. Following are some key features of system generator :-

• Using industry’s most advanced FPGAs, system generator develop highly parallel systems.

• With the help of Simulink and MATLAB, system generator provides modeling and generates HDL codes automatically.

• System generator produces integration of hardware component of DSP system, RTL, embedded, IP, and MATLAB.

System Generator

With the help of System Generator, designers which have a little design experience on FPGAs can quickly design good quality FPGAs of DSP algorithm in a fraction of time as compared to traditional RTL.

System generator accelerates design with simulation by leveraging the combination of System Generator for DSP design environment with latest release of the Vivado Design suit with following features.
• Provide support for 20nm All Programmable ASIC-class architecture.

• Provide support for Hardware Co-simulation for the KC705 and VC707 prototyping platforms allows for more simulation cycles in one iteration.

• By passing data through FIFO and BRAM facilitate a complete system level design and this support for multiple asynchronous clock domains.

• By using cross probe between a model and the waveform viewer enables quick debugging and verification.

Xilinx DSP Design Platform is integrated with Vivado IDE, IP catalog and High-Level Synthesis. System generator quickly imports Vivado IP for modeling with Simulink. It incorporates a DSP algorithm into All Programmable SoCs or FPGAs of Xilinx. Xilinx blockset are useful to design and debug high performance DSP system in Simulink that contain signal processing function, error correction, memories and digital logic. Best part of System generator is that it automatically generates HDL codes from Simulink implement behavioral (RTL). Code generation and hardware co-simulation feature provide option of validation of working hardware. System generator accelerates simulations in MATLAB and Simulink.


Author - Poornima Sharma
(Intern at Silicon Mentor)
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