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2
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1
answer
210
views
Handling PCIe INTx interrupts (Virtual Wire Signaling) for AHCI without MSI/MSI-X (PIC-only mode)
I am writing an AHCI driver for a minimal kernel and need to handle PCIe interrupts without MSI, relying solely on the legacy PIC 8259 and PCIe INTx virtual wire signaling.
I have already implemented ...
1
vote
1
answer
91
views
Linux PCI pcibios_window_alignment() not working as intended after kernel upgrade
Currently I've been working and stuck on the job of upgrading Linux Kernel from 4.19 to 5.15.
There's source code that in kernel/arch/.../our_pci.c, my former coworker left pcibios_window_alignment() ...
0
votes
0
answers
46
views
Detecting a PCIe device PRSNT1# and PRSNT2# are disconnected
I designed a defective PCIe device that PRSNT1# and PRSNT2# are disconnected by accident. Interestingly, most of the motherboards were ABLE to detect this device (that's why I found this issue so late)...
0
votes
1
answer
55
views
Get PCI address given a `struct net_device *`
In Linux kernel space, given a struct net_device * how can I get the associated PCI address?
0
votes
1
answer
294
views
QEMU VFIO noiommu mode: Error accessing /dev/vfio/0 despite using noiommu-0 device
I enabled VFIO's noiommu mode, and after binding the device to the VFIO driver, I see noiommu-0 under /dev/vfio/. Then, I try to pass the device through to a VM on QEMU, but QEMU throws an error ...
0
votes
1
answer
201
views
Is there any common PCIe DMA memcpy function in Linux
I meet the same problem with this guy
Memcpy from PCIe memory takes more time than memcpy to PCIe memory
Yes, MMIO read is very slow at x86/x86-64, only create/send the 32 or 64 bits of TLP payload ...
1
vote
0
answers
48
views
Linux PCI iomem catch mem access errors in device driver
I have device on embedded CPU ls1043 running OS Linux (custom build on 4.14 kernel). CPU connected to FPGA with PCI 3.0 x1.
In FPGA only BAR 0 with all internal register space. But, not all addresses ...
0
votes
1
answer
316
views
PCI Express AER driver doesn't insert /dev/aer_inject as device
Currently using the description shown at this site to capture PCI-e AER codes.
All the options related to the custom kernel compilation has been enabled as shown below
cat /boot/config-6.8.0-48-...
0
votes
1
answer
97
views
Problem with understanding IDE driver initialization
While developing an ATA PIO driver, I followed these tutorials: PCI IDE Controller and ATA PIO Mode. I successfully implemented a simple, minimal driver in QEMU for i386. However, I decided to ...
1
vote
0
answers
243
views
The correct way to initialize PCI device manually
A Linux kernel PCI device driver would usually call pci_register_driver() and get a callback via ->probe(). In this callback we would use pci_enable_device(), pci_set_master() and finally ...
1
vote
0
answers
174
views
How to find type of PCI slots on windows server
I want to get PCI slot type information on windows similar to linux.
On Linux when I run
dmidecode -t slot
I see output similar to
# dmidecode 3.3
Getting SMBIOS data from sysfs.
SMBIOS 3.2.1 present.
...
0
votes
0
answers
168
views
How to create a PCI node in devicetree for server platforms?
Our goal is to boot linux kernel using devicetree. Implementation like bootloader pass dtb file to linux to enumerate pci and stuffs ...
In our server platforms we have multiple segments and multiple ...
0
votes
0
answers
635
views
How to get PCI slot information for network adapters / NIC cards using python API like wmi on windows
On windows I want to find which network adapter in which slot.
I found following powershell commands.
Get-WmiObject -class "Win32_SystemSlot" which gives pci slot information
...
1
vote
1
answer
459
views
Enabled MSI in qemu, but interrupt handler not invoking
I'm trying to build my own OS following a certain tutorial book.
(For the reference, it is a Japanese book called "ゼロからのOS自作入門".
Its source code is available here but I'm using Rust instead ...
0
votes
2
answers
1k
views
Since PCIe write TLP is Post, what will happen when CPU access memory mapped bar address very frequently?
Since PCIe write is a Post TPL, what will happen when CPU tries to write to a memory mapped BAR address very frequently?
For example, write a busy loop and update a Register on a PCIe device.
When the ...