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2 votes
0 answers
81 views

I have a few questions regarding the structure and operation of the LFB. I am specifically interested in how x86 processors, or if more specialization is needed, 64-bit Intel processors post-haswell ...
Advice
0 votes
2 replies
96 views

I have some troubles with prebuilt development tools (compiler, linker, ...) on my very old workstation. Because the CPU from my old system only supports the micro architecture level x86-64-v1 it ...
1 vote
1 answer
112 views

Short background: MMIO regions are typically mapped as uncachable / device memory, so CPU must not treat device registers like normal cacheable DRAM. I’m asking about the microarchitecture routing and ...
0 votes
0 answers
112 views

I'm looking at computer microarchitecture and understanding how CPUs work in hope to perhaps design my own CPU out of logic gates. I understand that the complex nature of x86-64 instructions having ...
0 votes
1 answer
99 views

When a mem access occurs and the accessed bit in the PT is 0, it triggers a microcode assist that walks the PT and sets the accessed bit in each level. In oredr for the assist's code to write the ...
3 votes
0 answers
152 views

Motivation I'm working on improving the performance of a numerical simulation engine. This mainly involves re-organizing the memory layouts and access patterns in several ways, re-writing the inner ...
4 votes
2 answers
201 views

Given the following C program (MSVC does not optimize away the "work" for me, for other compilers you may need to add an asm statement): #include <inttypes.h> #include <stdlib.h> ...
1 vote
1 answer
857 views

I am learning rocketchip these days, and I have noticed the IFU(Instruction Fetch Unit) fetches instructions from ibuf instead of main memory. But I have not seen any codes about how instructions are ...
6 votes
1 answer
306 views

In the document titled Data Operand Independent Timing Instruction Set Architecture (ISA) Guidance Intel is introducing a new IA32_UARCH_MISC_CTL MSR where toggling bit 0 enables the "Data ...
-1 votes
1 answer
208 views

I'm trying to code a riscv decoder in system verilog, here's the code : case(opcode) 7'b0110011: assign r_type = 1'b1; 7'b0010011: assign i_type = 1'b1; 7'b0000011: ...
3 votes
0 answers
179 views

I'm tunning my program for low-latency. I have a tight calculation function calc(); which is using SIMD floating point instructions heavily. I had test the performance of calc(); using perf command. ...
1 vote
1 answer
170 views

There are two identical memory read ports (port 2 and 3) and one write port (port 4) of Intel Skylake cores. Assuming there are two load instructions issued to port 2 and port 3 parallelly: When both ...
1 vote
1 answer
194 views

Is assembly code and machine code specified by the architecture? I know that how you implement the architecture is up to you (the microarchitecture can implement the architecture), but I don't ...
-1 votes
1 answer
730 views

So, I have this assignment where I need to design a RISC-32-bit 5 stage pipeline. I must support at least 32 (32-bit) instructions and 32 (32-bit) data values. The memory should be read in 1 clock ...
1 vote
1 answer
92 views

Going to sleep tonight I have been wondering: if bool, in C++ for example, is set to false that mean, that all of it’s (8 or 16)bits are set 0(seems to be). Zero bit, as far as I know, means no ...

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