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Tooling
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64
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simulating aarch64 (ARM 64 bit)branch predictor unit (BPU)
I am working on a microarchitectural tooling project, and as part of a heuristic I need the ability to observe and manipulate the internal state of a branch predictor. Specifically, I am looking for ...
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52
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gem5 Cache Prefetcher Assertion Failure in sendMSHRQueuePacket: Prefetch Request Sent for an Existing Cache Line
I'm currently using gem5-dpdk (GitHub) with the following cache hierarchy setup:
Using ARM version(O3 cpu), full system mode
Simulating DPDK network application (e.g., MACSWAP)
L1 Cache: no ...
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How to dump statistics in gem5 when the execution is aborted?
I'm interested in having the stats.txt file produced in any condition, even if the execution gets aborted.
I am not an expert in gem5 and I'm really struggling to find useful information in the ...
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1
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114
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How are MMIO requests routed in CPU microarchitecture — cache-bypass on same path or a separate bus/port?
Short background: MMIO regions are typically mapped as uncachable / device memory, so CPU must not treat device registers like normal cacheable DRAM. I’m asking about the microarchitecture routing and ...
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Directing scons to link local instal of a library instead of system version
I have an obsolete system installation of a library (yaml-cpp) on an RPM Linux for which I do not have admin permissions. This library is a dependency for a some custom code that I am writing for a ...
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25
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Errors while executing SPEC2006 in gem5 with SPARC ISA
I run several benchmarks of SPEC2006 in gem5 version 24.1.0.3 in SPARC isa. But all time i am getting the same error:src/sim/syscall_emul.cc:79: fatal: syscall set_tid_address (#166) unimplemented.
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105
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How do I setup SME on Gem5?
I am performance testing kernels on Gem5 24.1.0.2, where I am trying to use SME intrincics to run with Gem5.
armclang -march=armv9.2-a+sme g2.c -o g2
./build/ARM/gem5.opt --stats-file=stats.txt --...
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37
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How to collect instruction traces that can be used by the gem5 simulator?
I want to analyze the impact of different microarchitecture designs on a certain workload, so I would like to collect traces on a machine running that workload and use those traces in the gem5 ...
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83
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Why cannot build gem5 with a custom memory controller?
I'm trying to integrate a custom memory controller in gem5 but when I try to build it returns me this error:
terminate called after throwing an instance of 'pybind11::error_already_set'
what(): ...
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40
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Couldn't parse 'cont_choice "Ruby protocol"' on Gem5
I need Ruby cache on my gem5 simulation. I have followed the ruby-intro-chapter documentation. On section
Compiling a protocol with SCons
/ In the newer gem5 version (gem5 >= 23.1),
when I run,
...
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0
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70
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where is directory memory of dir controller of cache coherence protocol stored in real chip?
In the MESI_Three_Level protocol of GEM5 simulator, there are L0, L1, L2, dir and dma state machines. L0 and L1 cache controllers simulate private caches for processor cores, which are implemented ...
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71
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Assembly : error concerning which type of register is used
I am assigned to make an assembly code that does the following task :
Write an assembler program that is given a parameter n∈{0,1,...,58} and iteratively determines the nth TUDO number in a loop. The ...
1
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0
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131
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Spec '06 benchmarks on Gem5: Increasing stack size by one page
I am trying to run the Spec '06 benchmarks on Gem5. All of the benchmarks I've tried seem to start up normally and then output the following and stall indefinitely:
src/sim/mem_state.cc:448: info: ...
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1
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327
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Compile gem5 ends with no binary file but no error
there! I am compiling gem5 according to the very simple tutorial on their webpage. However, I fail to finish this. It shows that I cannot link an .opt file at the end. I will list the env I used and ...
-1
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1
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90
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Configure latency parameters for CPU cache hit/miss latency in Gem5
I'm configuring the hit latency for a CPU model in Gem5. While I notice there are many latency parameters(eg. tag_latency, data_latency, frontend_latency, forward_latency, response_latency) which are ...