Makefile conditional OR for definitions

Question

I have a Makefile with 2 ifdef conditions that perform same action when that particular config is selected.

 #ifdef A
 //perform C
 #endif /* A */
 #ifdef B
 //perform C
 #endif /* B */
 #ifdef A || B
 //perform C
 #endif

Last code block is not working. What is the right way to execute it in Makefile?

• Andreas: In GNU Make, lines starting with # are comments. Should probably fix that.
• Andreas: Found nothing obvious in the docs. You could define a PERFORM_C variable, then conditionally undefine it in nested ifndef A/ifndef B, then follow up with a ifdef PERFORM_C that performs C. Not great, just my 2 cents.

Answer 1

#ifdef and #endif are not make conditionals. You probably want:

ifdef A
# whatever if make variable A is defined
AB := defined
endif
ifdef B
# whatever if make variable B is defined
AB := defined
endif
ifeq ($(AB),defined)
# whatever if the make variable A or B is defined
endif

Note that ifdef A is not the same as ifneq ($(A),). So, if you want to test these variables not for definition but for emptiness, you probably want:

ifneq ($(A),)
# whatever if the value of make variable A is non-empty
endif
ifneq ($(B),)
# whatever if the value of make variable B is non-empty
endif
ifneq ($(A)$(B),)
# whatever if the value of make variable A or B is non-empty
endif

Answer 2

Here's one way to do it using a variant of the technique I proposed in a comment:

# De Morgan's Law: (!a && !b) == !(a || b)
ifndef A
 ifndef B
 NEITHER_A_NOR_B_DEFINED :=
 endif
endif
ifndef NEITHER_A_NOR_B_DEFINED
 # Perform C
endif