Signal initialization VHDL

Question

I have an entity which has this

TEMPERATURE: in STD_LOGIC_VECTOR(7 downto 0);

as one of the inputs and I need a signal that has the initial value TEMPERATURE. In the entity architecture I've declared the signal

signal temp:STD_LOGIC_VECTOR(7 downto 0):=TEMPERATURE;

but when simulating temp remains UU(unassigned). How do I fix this?

• JHBonarius: Welcome to SackOverflow. We do not know what TEMPERATURE is and are missing a lot of context. Please provide a minimal reproducible example.
• Paebbels: At simulation startup, TEMPERATURE is all 'U'. Thus, temp gets initialized to all 'U'. 'U' stands for uninitialized, not unassigned. You should either initialize temp from a (generic) constant or implement a flip-flop. Your current design will not synthesize as expected.
• user1818839: You find ALL the drivers on that signal and either initialise or disconnect them.
• Matthew: This sounds like an XY problem. If this is your design, you shouldn't be initialising a signal from an input at all. So, instead of trying to initialise temp to TEMPERATURE, I would take a step back and consider what it is you are trying to achieve (and what hardware you expect to be synthesised).