🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.
Microarchitecture impact analysis using gem5 - Computer Architecture course project - Computer Science @ FAMAF (UNC)
Procesor ve VHDL pro jazyk Brainfuck
Forth translator & CISC processor model
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