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processor-architecture

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intel / pcm

Intel® Performance Counter Monitor (Intel® PCM)

windows linux freebsd processor-architecture energy cpu monitoring osx processor intel performance-metrics power xeon performance-visualization performance-dashboard pcm performance-analysis monitor-performance performance-monitoring performance-counters

Updated Aug 11, 2025
C++

mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

education processor-architecture qt simulator computer-architecture risc risc-v cpu-emulator

Updated Aug 22, 2025
C++

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Nov 8, 2024
C

hlorenzi / customasm

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

rust processor-architecture vm bytecode compiler custom virtual-machine assembly asm assembler webassembly rust-lang customizable assembly-language microprocessor instruction-set-architecture machine-code bytecode-compiler instruction-set user-defined

Updated Jul 20, 2025
Rust

mikeroyal / RISC-V-Guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

processor-architecture simulator processor virtualization hypervisor optimize platformio riscv peripherals android-app computer-architecture cpu-profiling sbc risc-v sel4 risc-processor rv32 riscv64 tensoflow-lite riscv-emulator

Updated Jan 4, 2024
Assembly

Mariotti94 / WebRISC-V

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Jun 8, 2025
PHP

jmuehlig / perf-cpp

Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.

linux processor-architecture library performance cpp perf performance-metrics cpp17 performance-analysis sampling performance-monitoring system-programming performance-counters performance-measurement performance-analyses instruction-based-sampling processor-event-based-sampling

Updated Aug 22, 2025
C++

sstsimulator / sst-elements

SST Architectural Simulation Components and Libraries

processor-architecture simulator networking simulation hpc memory cache processor trace network-analysis cache-simulator system-design snl-other snl-performance-workflow

Updated Aug 26, 2025
C++

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

Updated Jun 5, 2025
SystemVerilog

caleb531 / cache-simulator

A processor cache simulator for the MIPS architecture

python processor-architecture simulator mips cache processor

Updated Jul 10, 2025
Python

physical-computation / sunflower-embedded-system-emulator

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

processor-architecture simulator embedded-systems j-core riscv cross-compiler network-simulator emulators processor-simulator superh hitachi riscv32 battery-simulator power-simulator riscv-sim riscv-simulator riscv-emulator

Updated Jan 31, 2025
C

alirezakay / RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

processor-architecture cpu vhdl isa cpu-model instruction-set-architecture mips-processor vhdl-modules risc-processor vhdl-code cpu-architecture multi-cycle processor-design

Updated Jun 19, 2021
VHDL

sdasgup3 / parallel-processor-design

Super scalar Processor design

processor-architecture bison flex processor assembler parallel-computing verilog forwarding bypassing pipeline-processor superscalar opcode verilog-hdl instruction-set-architecture instruction-set processor-simulator branch-prediction pipeline-cpu mnemonics instruction-level-parallelism

Updated Sep 7, 2014
Verilog

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

computer-science processor-architecture engineering computer-engineering textbooks computer-organization computer-organisation processor-design computer-organisation-architechure computer-organization-lab computer-organization-and-design computer-organ ameythakur amey megasatish

Updated Mar 13, 2024
C

alexander-titov / public

A collection of my cources, lectures, articles and presentations

computer-science processor-architecture lectures cpu presentations computer-engineering computer-architecture digital-design

Updated Jun 25, 2019
C++

ShichenQiao / ECE554_SP23_FPGA_Handwriting_Recognition

Senior Design Project at UW-Madison ECE

processor-architecture fpga cnn handwriting-recognition

Updated May 4, 2023
Verilog

GodTamIt / tomasulo-simulation

A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.

processor-architecture hardware simulation processor processor-simulator tomasulo

Updated Apr 22, 2017
C++

prantoamt / 16bit_processor_design

processor-architecture cpu mips simulation processor cse mips-assembly hardware-designs computer-architecture mips-assembler logisim mips-language mips-architecture mips-processor mips-simulator computer-design-and-implementation cse332

Updated Dec 30, 2018

Mograsim-Team / Mograsim

Modular Graphical Simulator for Teaching Microprogramming

plugin java emulator processor-architecture modular simulator tum amd eclipse processor emulation assembler teaching graphical instruction-set-architecture microprogramming processor-simulator era am2900 mograsim

Updated Dec 16, 2024
Java

GeekAlexis / superscalar-mips

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

processor-architecture mips verilog

Updated Nov 28, 2019
Verilog

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