ibex

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

• Updated Aug 28, 2023
• SystemVerilog

Testing Ibex build using Yosys and open source toolchains.

• Updated Oct 2, 2021
• Shell

User oriented Portfolio optimization application with several configuring options. Back test included. (IBEX35; to be expanded)

• Updated Aug 26, 2018
• Jupyter Notebook

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

• Updated Jul 3, 2022
• Python

An example project that utilizes caravel user space for an ibex based SoC

• Updated Aug 16, 2021
• Verilog

RISC-V Ibex core with Wishbone B4 interface

• Updated Apr 26, 2020
• C

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

• Updated Jul 15, 2026
• SystemVerilog

Terraform and Packer Boilerplate code with a nifty script to simplify infrastructure creation

• Updated Apr 10, 2019
• Ruby

Master 2 robotic project : viewing calibration concepts, path planing and trajectory following. Using library Ibex with python to represent robots geometric and kinetic models

• Updated Dec 16, 2018
• Python

GPU-accelerated Python data science project scaffold for PyTorch and KAUST Ibex workflows

• Updated Jul 23, 2024
• Python

Created in 2020. A self-paced reading task (followed by comprehension questions). Sentence materials borrowed from Chow & Chen (2020)

• Updated Dec 12, 2021
• JavaScript

Incremental unidirectional and bidirectional graph transformations with the Democles pattern matching engine

• Updated Jun 14, 2024
• Java

Open-source industrial EMS for PV, BESS, markets and Edge control. / Open-source индустриална EMS за PV, BESS, пазари и Edge управление.

• Updated Sep 8, 2026
• TypeScript

Artifact for compositional verification of PMP–IOPMP isolation in RISC-V SoCs, including real-Ibex validation, reset-ordering analysis, formal verification, simulation, and SKY130HD PPA evaluation.

• Updated Aug 14, 2026
• SystemVerilog

Ibex RV32 custom-instruction integration and PQC bare-metal porting experiments with Verilator

• Updated Sep 7, 2026
• C

Created in Feb 2020. A self-paced reading task interleaving with the Stroop task. Experimental design: 2 previous trial congruency (congruent Stroop vs. incongruent Stroop) x 2 current trial ambiguity (ambiguous sentence vs. unambiguous sentence). Wrote on PCIbex.

• Updated Dec 12, 2021
• JavaScript

One event, followed down every layer of the machine, on one clock — C source to switching Sky130 standard cells, in one HTML file.

• Updated Sep 6, 2026
• Verilog

Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV

• Updated Oct 4, 2022
• SystemVerilog

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

• Updated Jul 20, 2026
• SystemVerilog

OpenTitan Rv Core Ibex IP block

• Updated Sep 7, 2026
• SystemVerilog