Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
A Computer Organization and Architecture project implementing a 5-stage RV32I pipeline with BTB-based branch prediction, RTL design files, testbenches, simulation files, memory files, and documentation.
Landing page for a submarine and boat maker π’
VBS script to calculate the position of the sun according to the GPS position, date and time then create a settings.ini file for the Richard Burns Rally track in Bob Track's Builder format.
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