AXI4-Lite Protocol Checker

A SystemVerilog verification environment for an AXI4-Lite register-file DUT, built incrementally across six stages. The project demonstrates industry-standard verification practices: 5-channel monitoring, an associative-array scoreboard, SVA protocol assertions, functional coverage, back-pressure testing, and a dedicated negative-protocol testbench.

AXI4-Lite is a simplified subset of the ARM AMBA AXI4 bus protocol designed for single-beat (non-burst) register-level transactions. It uses five independent handshake channels: AW (write address), W (write data), B (write response), AR (read address), and R (read data).

This project verifies a simplified AXI4-Lite register-file slave (DUT) by:

• Observing all five channels via a passive monitor.
• Comparing observed read data against an in-memory reference model (scoreboard).
• Checking structural protocol rules through SystemVerilog Assertions (SVA).
• Measuring verification completeness via functional coverage.
• Stress-testing the DUT under legitimate master back-pressure.
• Deliberately injecting protocol violations and verifying the correct assertions fire.

AXI4-Lite-Protocol-Checker/
├── rtl/
│ └── axi_lite_dut.sv # DUT: 256-word register-file slave
├── tb/
│ ├── axi_lite_tb.sv # Positive testbench (SVA + coverage)
│ ├── axi_lite_neg_tb.sv # Negative protocol violation testbench
│ ├── axi_lite_driver.sv # Master driver with back-pressure
│ ├── axi_lite_monitor.sv # 5-channel passive transaction monitor
│ └── axi_lite_scoreboard.sv # Associative-array reference model
├── sim/
│ ├── run_regression.sh # Regression runner script (WSL/bash)
│ └── wave.do # Vivado waveform configuration
├── docs/
│ └── assets/
│ └── AXI_lite_write_read_waveform.png
├── Makefile # Build & run Makefile
├── run_regression.sh # Root-level regression entrypoint
├── .gitignore
└── README.md

+-------------------+ +---------------------+
| tb/axi_lite_tb | | tb/axi_lite_neg_tb |
| (Positive Tests) | | (Negative Tests) |
+-------------------+ +---------------------+
 | |
 +-----+-----+ +----------+----------+
 | | | | |
+--------+ +------+ +------+ +-------+ +------+
| Driver | | DUT | | DUT | | Mon. | | SB |
+--------+ +------+ +------+ +-------+ +------+
 | 
 +--------+ 
 | Mon. | 
 +--------+ 
 |
 +--------+ 
 | SB | 
 +--------+ 
SVA Assertions: 13 properties in tb/axi_lite_tb.sv (VALID/READY stability,
 address/data stability, no-X checks, response ordering).
Functional Coverage: Covergroup in tb/axi_lite_tb.sv (handshakes, address
 ranges, data patterns, stall/backpressure, cross).

• 5-Channel Monitoring: All AW, W, B, AR, R channels passively observed.
• Associative-Array Scoreboard: Reference memory mirrors DUT state; all reads are compared against predicted values without hardcoded expected data.
• 13 SVA Protocol Assertions: VALID stability, address/data stability, no-X/Z checks, write-response ordering, read-response ordering.
• Functional Coverage: Handshakes, address ranges (min/max), data patterns (all-zeros, all-ones, 0xAAAAAAAA, 0x55555555), backpressure stall bins, simultaneous AW/W cross coverage (100% closed).
• Legitimate Back-Pressure: Driver introduces 2-cycle delays on BREADY and RREADY, exercising the B/R stability assertions and stall coverage bins.
• Negative Protocol Testing: 4 targeted protocol violations injected and each detected by its intended assertion; gracefully tracked without crashing.
• Automated Regression: run_regression.sh and Makefile compile, elaborate, simulate, collect coverage, and exit with 0 (PASS) or 1 (FAIL).
• Waveform Debugging: sim/wave.do configures all 5 AXI channels and scoreboard signals for Vivado XSIM waveform view.

Each transaction: write (AW+W), wait for B response, read (AR), wait for R response. The 2-cycle back-pressure on BREADY/RREADY exercises stability assertions and stall bins.

• Transactions: 4 write/read pairs
• Scoreboard: 4 writes tracked, 4 reads checked, 4 PASS, 0 FAIL
• SVA assertions: 0 unexpected failures
• Exit code: 0

• 4 violations injected, 4 intended assertions detected
• No unrelated assertions fired
• Exit code: 0

AXI4-Lite Simulation Waveform

# From repository root:
chmod +x run_regression.sh
./run_regression.sh
# To clean artifacts and run clean regression:
./run_regression.sh --clean

make all # Runs positive + negative tests + generates coverage report
make sim # Runs positive testbench only
make neg # Runs negative testbench only
make cov # Generates text coverage report
make clean # Cleans generated simulation artifacts

xvlog -sv rtl/axi_lite_dut.sv tb/axi_lite_driver.sv tb/axi_lite_monitor.sv \
 tb/axi_lite_scoreboard.sv tb/axi_lite_tb.sv
xelab -debug all work.axi_lite_tb -s axi_sim
xsim axi_sim -runall

xvlog -sv rtl/axi_lite_dut.sv tb/axi_lite_monitor.sv \
 tb/axi_lite_scoreboard.sv tb/axi_lite_neg_tb.sv
xelab -debug all work.axi_lite_neg_tb -s axi_neg_sim
xsim axi_neg_sim -runall

xsim axi_sim -gui
# In Tcl console:
source sim/wave.do
run 2500ns

• Simulator: AMD/Xilinx Vivado XSIM (tested with v2025.2)
• Language: SystemVerilog (IEEE 1800-2017)
• Environment: Linux / WSL2 (Ubuntu) / Windows compatible

This is a simplified educational DUT, not a full production AXI4-Lite slave:

• No WSTRB (write strobe) — all 4 bytes are written unconditionally.
• No BRESP / RRESP (response status codes).
• No AWPROT / ARPROT (protection signals).
• Address decode uses only bits [7:0] (256-word depth).
• AW and W channels are expected simultaneously.
• W-before-AW ordering is not supported.

Verification assertions and coverage reflect what this DUT actually implements. No coverage was artificially forced to 100% by relaxing correctness criteria.

Ansh Verma