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Create README.md

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	`1`	`+# RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg`
	`2`	`+Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..`
	`3`	`+Here we are using Vivado HLx software to generate bitstream for Basys3 kit and using Artix-7.`
	`4`	`+I have also shared .xdc file for basys3.You have to customize .xdc file according to your requirement.`

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