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Commit d9da6dd

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‎ALU.v

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module ALU #(parameter Width = 32)(
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input [3:0] controlsignal, input [Width-1:0] A1,A2,
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output reg [Width-1:0] Y, output zero);
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//wire [63:0] B;
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always @(*)
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begin
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if (controlsignal == 4'b0000)
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Y = A1 & A2;
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else if (controlsignal == 4'b0001)
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Y = A1 | A2;
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else if(controlsignal == 4'b0010)
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Y = A1 + A2;
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else if(controlsignal == 4'b0110)
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Y = A1 - A2;
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else if(controlsignal == 4'b0011)
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Y = A1 << A2;
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else if(controlsignal == 4'b0100)
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begin
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//A1 = ~A1 + 1;
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//A2 = ~A2 + 1;
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if((~A1+1) < (~A2+1))
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Y = 1;
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else
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Y = 0;
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end
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else if(controlsignal == 4'b0101)
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begin
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if(A1 < A2)
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Y = 1;
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else
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Y = 0;
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end
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else if(controlsignal == 4'b0111)
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Y = A1 ^ A2;
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else if(controlsignal == 4'b1000)
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Y = A1 >> A2;
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else if(controlsignal == 4'b1010)
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Y = A1 >>> A2;
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else
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Y = {Width{1'bx}};
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end
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assign zero = (Y == 0) ? 1 : 0;
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endmodule

‎ALUControl.v

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`timescale 1ns/1ps
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module ALUControl(
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input [1:0] Aluop,
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input funct7,[2:0] funct3,
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output reg [3:0] Control);
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always @(*)
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begin
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case (Aluop)
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2'b00 : Control <= 4'b0010;
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2'b01 : Control <= 4'b0110;
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2'b10 : case({funct7,funct3})
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4'b0000 : Control <= 4'b0010; // add
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4'b1000 : Control <= 4'b0110; // sub
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4'b0111 : Control <= 4'b0000; // and
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4'b0110 : Control <= 4'b0001; // or
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4'b0001 : Control <= 4'b0011; // sll
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4'b0010 : Control <= 4'b0100; // slt
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4'b0011 : Control <= 4'b0101; // sltu
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4'b0100 : Control <= 4'b0111; // xor
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4'b0101 : Control <= 4'b1000; // srl
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4'b1101 : Control <= 4'b1010; // sra
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default : Control <= 4'bxxxx;
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endcase
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2'b11 : case({funct7,funct3})
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4'b0000 : Control <= 4'b0010; // addi
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4'b0010 : Control <= 4'b0100; // slti
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4'b0011 : Control <= 4'b0101; // sltui
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4'b0100 : Control <= 4'b0111; // xori
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4'b0110 : Control <= 4'b0001; // ori
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4'b0111 : Control <= 4'b0000; // andi
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4'b0001 : Control <= 4'b0011; // slli
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4'b0101 : Control <= 4'b1000; // srli
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4'b1101 : Control <= 4'b1010; // srai
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default : Control <= 4'bxxxx;
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endcase
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endcase
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end
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endmodule

‎Adder.v

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module adder #(parameter Width = 32)(
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input [Width-1:0] PC,
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output [Width-1:0] PCPlus4);
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assign PCPlus4 = PC + 1;
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endmodule

‎Architecture Block diagram.jpg

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‎DataMemory.v

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module DataMemory #(parameter Width = 32)
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(input clk,MemWrite,MemRead, [Width-1:0] ALUResult,WriteData, //WriteData=RD2
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output [Width-1:0] ReadData);
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reg [Width-1:0] mem1[511:0];
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initial
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begin
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mem1[0] = 32'h00000000;
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mem1[1] = 32'h00000000;
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mem1[2] = 32'h00000000;
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mem1[3] = 32'h00000000;
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mem1[4] = 32'h00000000;
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mem1[5] = 32'h00000000;
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mem1[6] = 32'h00000000;
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mem1[7] = 32'h00000000;
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mem1[8] = 32'h00000000;
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mem1[9] = 32'h00000000;
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mem1[10] = 32'h00000000;
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mem1[11] = 32'h00000000;
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mem1[12] = 32'h00000000;
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mem1[13] = 32'h00000000;
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mem1[14] = 32'h00000000;
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mem1[15] = 32'h00000000;
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mem1[16] = 32'h00000000;
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mem1[17] = 32'h00000000;
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mem1[18] = 32'h00000000;
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mem1[19] = 32'h00000000;
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mem1[20] = 32'h00000000;
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mem1[21] = 32'h00000000;
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mem1[22] = 32'h00000000;
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mem1[23] = 32'h00000000;
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mem1[24] = 32'h00000000;
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mem1[25] = 32'h00000000;
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mem1[26] = 32'h00000000;
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mem1[27] = 32'h00000000;
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mem1[28] = 32'h00000000;
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mem1[29] = 32'h00000000;
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mem1[30] = 32'h00000000;
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end
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always @(posedge clk)
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begin
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if(MemWrite==1'b1)
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mem1[ALUResult] <= WriteData;
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end
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assign ReadData = (MemRead==1'b1) ? mem1[ALUResult]: 32'd0;
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endmodule

‎ImmediateGeneration.v

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module immediategeneration #(parameter Width = 32)(
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input [1:0]immsrc,[31:0] instr,
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output reg [Width-1:0] extimm);
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always @(*)
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begin
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case(immsrc)
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//R-type has no immediate
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2'b 00:extimm={{20{instr[31]}},instr[31:20]}; //I type
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2'b 01:extimm={{21{instr[31]}},instr[30:25],instr[11:7]};//S type
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2'b 10:extimm={{20{instr[31]}},instr[7],instr[30:25],instr[11:8],1'b0};//B type
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2'b 11:extimm={{12{instr[31]}},instr[19:12],instr[20],instr[30:21],1'b0};//U type
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default:extimm=32'bx;
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endcase
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end
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//assign Out = {{52{In[31]}},In[31:20]};
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endmodule

‎Instructionmemory.v

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module instructionmemory(PC, RD);
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input [31:0]PC;
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output [31:0] RD;
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reg [31:0] mem1[511:0];
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initial
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begin
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mem1[0] = 32'h00000113;
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mem1[1] = 32'h00000113; //addi x2 0(x0)
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mem1[2] = 32'h00400093; //addi x1 4(x0)
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mem1[3] = 32'h00100193; //addi x3 1(x0)
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mem1[4] = 32'hFE20AF23; //sw x2 -2(x1)
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mem1[5] = 32'hFE30AFA3; //sw x3 -1(x1)
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mem1[6] = 32'h00310233; //add x4 x2 x3
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mem1[7] = 32'h0040A023; //sw x4 0 (x1)
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mem1[8] = 32'h00108093; //addi x1 1 (x1)
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mem1[9] = 32'h00018113; //addi x2 0 (x3)
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mem1[10] = 32'h00020193; //addi x3 0 (x4)
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mem1[11] = 32'h00310233; //add x4 x2 x3
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mem1[12] = 32'h0040A023; //sw x4 0 (x1)
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mem1[13] = 32'h00108093; //addi x1 1 (x1)
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mem1[14] = 32'h00018113; //addi x2 0 (x3)
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mem1[15] = 32'h00020193; //addi x3 0 (x4)
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mem1[16] = 32'h00310233; //add x4 x2 (x3)
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mem1[17] = 32'h0040A023; //sw x4 0(x1)
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mem1[18] = 32'h00108093; //addi x1 1 x1
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mem1[19] = 32'h00018113; //addi x2 0 x3
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mem1[20] = 32'h00020193; //addi x3 0 x4
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mem1[21] = 32'h00310233; //add x4 x2 x3
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mem1[22] = 32'h0040A023; //sw x4 0 x1
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mem1[23] = 32'h00108093; //addi x1 1 x1
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mem1[24] = 32'h00018113; //addi x2 0 x3
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mem1[25] = 32'h00020193; //addi x3 0 x4
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mem1[26] = 32'h00310233; //add x4 x2 x3
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mem1[27] = 32'h0040A023; //sw x4 0 x1
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mem1[28] = 32'h00108093; //addi x1 1 x1
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mem1[29] = 32'h00018113; //addi x2 0 x3
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mem1[30] = 32'h00020193; //addi x3 0 x4
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mem1[31] = 32'h00310233; //add x4 x2 x3
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mem1[32] = 32'h0040A023; //sw x4 0 x1
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mem1[33] = 32'h00108093; //addi x1 1 x1
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mem1[34] = 32'h00018113; //addi x2 0 x3
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mem1[35] = 32'h00020193; //addi x3 0 x4
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mem1[36] = 32'h00310233; //add x4 x2 x3
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mem1[37] = 32'h0040A023; //sw x4 0 x1
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mem1[38] = 32'h00108093; //addi x1 1 x1
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mem1[39] = 32'h00018113; //addi x2 0 x3
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mem1[40] = 32'h00020193; //addi x3 0 x4
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mem1[41] = 32'h00310233; //add x4 x2 x3
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mem1[42] = 32'h0040A023; //sw x4 0 x1
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mem1[43] = 32'h00108093; //addi x1 1 x1
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mem1[44] = 32'h00018113; //addi x2 0 x3
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mem1[45] = 32'h00020193; //addi x3 0 x4
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mem1[46] = 32'h00310233; //add x4 x2 x3
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mem1[47] = 32'h0040A023; //sw x4 0 x1
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mem1[48] = 32'h00108093; //addi x1 1 x1
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mem1[49] = 32'h00018113; //addi x2 0 x3
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mem1[50] = 32'h00020193; //addi x3 0 x4
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mem1[51] = 32'h00310233; //add x4 x2 x3
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mem1[52] = 32'h0040A023; //sw x4 0 x1
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mem1[53] = 32'h00108093; //addi x1 1 x1
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mem1[54] = 32'h00018113; //addi x2 0 x3
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mem1[55] = 32'h00020193; //addi x3 0 x4
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mem1[56] = 32'h00310233; //add x4 x2 x3
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mem1[57] = 32'h0040A023; //sw x4 0 x1
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mem1[58] = 32'h00108093; //addi x1 1 x1
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mem1[59] = 32'h00018113; //addi x2 0 x3
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mem1[60] = 32'h00020193; //addi x3 0 x4
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mem1[61] = 32'h00310233; //add x4 x2 x3
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mem1[62] = 32'h0040A023; //sw x4 0 x1
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mem1[63] = 32'h00108093; //addi x1 1 x1
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mem1[64] = 32'h00018113; //addi x2 0 x3
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mem1[65] = 32'h00020193; //addi x3 0 x4
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mem1[66] = 32'h00310233; //add x4 x2 x3
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mem1[67] = 32'h0040A023; //sw x4 0 x1
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mem1[68] = 32'h00108093; //addi x1 1 x1
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mem1[69] = 32'h00018113; //addi x2 0 x3
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mem1[70] = 32'h00020193; //addi x3 0 x4
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mem1[71] = 32'h00310233; //add x4 x2 x3
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mem1[72] = 32'h0040A023; //sw x4 0 x1
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mem1[73] = 32'h00108093; //addi x1 1 x1
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mem1[74] = 32'h00018113; //addi x2 0 x3
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mem1[75] = 32'h00020193; //addi x3 0 x4
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mem1[76] = 32'h00310233; //add x4 x2 x3
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mem1[77] = 32'h0040A023; //sw x4 0 x1
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mem1[78] = 32'h00108093; //addi x1 1 x1
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mem1[79] = 32'h00018113; //addi x2 0 x3
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mem1[80] = 32'h00020193; //addi x3 0 x4
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mem1[81] = 32'h00310233; //add x4 x2 x3
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mem1[82] = 32'h0040A023; //sw x4 0 x1
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mem1[83] = 32'h00108093; //addi x1 1 x1
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mem1[84] = 32'h00018113; //addi x2 0 x3
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mem1[85] = 32'h00020193; //addi x3 0 x4
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mem1[86] = 32'h00008093; //addi x1 0 x1
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//loading
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mem1[87] = 32'h00202303; //lw x7 2( x0)
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mem1[88] = 32'h00302303; //lw x7 3( x0)
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mem1[89] = 32'hFF00A483; //lw x7 -16( x1)
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mem1[90] = 32'hFF10A483; //lw x7 -15( x1)
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mem1[91] = 32'hFF20A483; //lw x7 -14( x1)
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mem1[92] = 32'hFF30A483; //lw x7 -13( x1)
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mem1[93] = 32'hFF40A483; //lw x7 -12( x1)
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mem1[94] = 32'hFF50A483; //lw x7 -11( x1)
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mem1[95] = 32'hFF60A483; //lw x7 -10( x1)
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mem1[96] = 32'hFF70A483; //lw x7 -9( x1)
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mem1[97] = 32'hFF80A483; //lw x7 -8( x1)
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mem1[98] = 32'hFF90A483; //lw x7 -7( x1)
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mem1[99] = 32'hFFA0A483; //lw x7 -6( x1)
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mem1[100] = 32'hFFB0A483; //lw x7 -5( x1)
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mem1[101] = 32'hFFC0A483; //lw x7 -4( x1)
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mem1[102] = 32'hFFD0A483; //lw x7 -3( x1)
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mem1[103] = 32'hFFE0A483; //lw x7 -2( x1)
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mem1[104] = 32'hFFF0A483; //lw x7 -1( x1)
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mem1[105] = 32'hFE4187E3; //beq x3 x4 mem1[87]
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end
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assign RD = mem1[PC];
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endmodule

‎MUX.v

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module MUX #(parameter Width = 32)(input [Width-1 : 0] a,b,
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input s,
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output reg [Width-1 : 0] out);
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always @(s or a or b)
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begin
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out = (s == 1'b0) ? a : b;
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end
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endmodule

‎MUX1.v

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module MUX1 #(parameter Width = 32)(input [Width-1 : 0] a,b,c,
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input [1:0] s,
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output reg [Width-1 : 0] out);
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always @(s or a or b or c)
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begin
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//assign out = (s == 2'b10) ? c : (s == 2'b01) ? b : a;
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if(s==2'b00)
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out=a;
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else if(s==2'b01)
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out=b;
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else if(s==2'b10)
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out=c;
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else
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out=32'h xxxxxxxx;
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end
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endmodule

‎PC Counter.v

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module PCCounter( clk, PCNext, PC);
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input clk;
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input[31:0]PCNext;
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output reg [31:0] PC;
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always@(posedge clk)
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begin
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PC <= PCNext;
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end
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initial begin
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PC=32'b0;
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end
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endmodule

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