Chisel (programming language)
Paradigms | Multi-paradigm: concurrent, functional, imperative, object-oriented |
---|---|
Family | Scala |
Developer | University of California, Berkeley |
First appeared | June 2012; 12 years ago (2012-06) |
Stable release | 3.6.0
/ April 14, 2023; 23 months ago (2023年04月14日) |
Typing discipline | Inferred, static, strong, structural |
Scope | Lexical (static) |
Implementation language | Scala |
Platform | Java virtual machine (JVM) JavaScript (Scala.js) LLVM (Scala Native) (experimental) |
Website | www |
Chisel (an acronym for Constructing Hardware in a Scala Embedded Language[1] ) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level.[2] [3]
Chisel is based on Scala as a domain-specific language (DSL). Chisel inherits the object-oriented and functional programming aspects of Scala for describing digital hardware. Using Scala as a basis allows describing circuit generators. High quality, free access documentation exists in several languages.[4]
Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation.
Code examples
[edit ]A simple example describing an adder circuit and showing the organization of components in Module with input and output ports:
classAddextendsModule{ valio=IO(newBundle{ vala=Input(UInt(8.W)) valb=Input(UInt(8.W)) valy=Output(UInt(8.W)) }) io.y:=io.a+io.b }
A 32-bit register with a reset value of 0:
valreg=RegInit(0.U(32.W))
A multiplexer is part of the Chisel library:
valresult=Mux(sel,a,b)
Use
[edit ]Although Chisel is not yet a mainstream hardware description language, it has been explored by several companies and institutions. The most prominent use of Chisel is an implementation of the RISC-V instruction set, the open-source Rocket chip.[5] Chisel is mentioned by the Defense Advanced Research Projects Agency (DARPA) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs.[6] Google has used Chisel to develop a Tensor Processing Unit for edge computing.[7] Some developers prefer Chisel as it requires 5 times lesser code and is much faster to develop than Verilog.[8]
Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation using a program named FIRRTL.[9] [better source needed ]
See also
[edit ]References
[edit ]- ^ Bachrach, J.; Vo, H.; Richards, B.; Lee, Y.; Waterman, A.; Avižienis, R.; Wawrzynek, J.; Asanović, K. (June 2012). "Chisel: constructing hardware in a Scala embedded language". Proceedings of the 49th Annual Design Automation Conference (DAC 2012). San Francisco, California, US: Association for Computing Machinery (ACM). pp. 1216–25. doi:10.1145/2228360.2228584. ISBN 978-1-4503-1199-1.
- ^ "Chisel". people.eecs.berkeley.edu. California, U.S.: University of California, Berkeley. Archived from the original on 2021年10月16日. Retrieved 2020年07月08日.
- ^ Bachrach, Jonathan (ed.). "Chisel: Accelerating Hardware Design" (PDF). RISC-V . California, U.S.: RISC-V International.
- ^ Schoeberl, Martin (August 30, 2019). Digital Design with Chisel (in English, Chinese, Japanese, and Vietnamese) (2nd ed.). Kindle Direct Publishing. ISBN 978-1689336031.
- ^ Asanović, Krste; et al. "rocket-chip". GitHub. RISC-V International. Retrieved 11 November 2016.
- ^ Moore, Samuel K. (2018年07月16日). "DARPA Plans a Major Remake of U.S. Electronics". IEEE Spectrum. Institute of Electrical and Electronics Engineers (IEEE). Retrieved 2020年06月10日.
- ^ Derek Lockhart, Stephen Twigg, Ravi Narayanaswami, Jeremy Coriell, Uday Dasari, Richard Ho, Doug Hogberg, George Huang, Anand Kane, Chintan Kaur, Tao Liu, Adriana Maggiore, Kevin Townsend, Emre Tuncer (2018年11月16日). Experiences Building Edge TPU with Chisel . Retrieved 2020年06月10日.
- ^ "XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 - CNX Software". CNX Software - Embedded Systems News. 2021年07月05日. Retrieved 2022年03月26日.
- ^ "Chisel/FIRRTL Hardware Compiler Framework" . Retrieved 2022年09月08日.