Questions tagged [ddr2]
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4
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1
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DDR2 CLK vs DSQ vs ADR length matching
I am tracing my first DDR2 with Cyclone V PCB and I can't find exact information about CLK vs DSQ vs ADR length matching.
External Memory Interface Handbook Volume 2: Design Guidelines from Intel says ...
0
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1
answer
2k
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
2
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1
answer
736
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Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
3
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1
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1k
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Why is On Die Termination (ODT) only available for Data Lines (DQ, DQS) but not for Address Lines in in DDR2/DDR3 memory?
I am trying to understand the need for termination resistors in DDR2/DDR3 designs and I have seen some Max 10 dev kit boards that don't terminate the address lines with 50 Ω terminating resistors.
...
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0
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How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
0
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1
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432
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Are reference resistors required for VRP and VRN when implementing an DDR2 memory controller in an Artix-7 device?
The generated pinout does not list any VRP or VRN pins, or anything similar.
I have specified internal impedance for the DDR2 IF pins with IO standard SSTL18_II. On previous and other FPGAs, it is ...
-2
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1
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480
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Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
4
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1
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524
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Why do DDR RAMs have both xDQ and xDM signals?
DDR2 RAMs have these control signals
RAS, CAS - address strobes
UDQ, LDQ - byte strobes
WE - write enable
UDM, LDM - write mask
Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
3
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3
answers
833
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
0
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1
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452
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Interfacing a RAM chip from a commercial computer with an ARM cpu such as Stm32
I need to interface some sort of RAM with an ARM processor for my embedded project. Around 128 MB to be exact. I found a computer RAM which claims to be DDR and 1 GB. As I only need 128 MB of RAM for ...
2
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0
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452
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DDR2 and DDR3 ODT and ZQ calibration
Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3??
Which method is very useful for DDR2 termination? whether ODT or External parallel termination??
...
1
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2
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167
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calibration working in DDR2/3 memory devices [closed]
Does anyone know exact working and what will be blocks present inside the calibration module of DDR2/3 memory devices?
Any information related to calibration process of DDR2/3 SDRAM's is appreciated.....
7
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3
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1k
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DDR(2-4) Training and Length Matching
Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being ...
2
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1
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745
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What is the more frequent error in DDR Memory?
this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
2
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1
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123
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Replacing a DDR2 memory with another that is faster
Are there any known timing issues with directly replacing on board one DDR2 SDRAM with another package and pin compatible DDR2 that is slightly faster?