I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work.
EDITION1: According to comments, I checked DONE situation after programming and it is in High state. Also added pull down resistors to a and b. Also added a 1KΩ pull down resistor to TMS. Now it works fine but after I restart the device, it does not work any more.It seems the configuration memory is erased after shut down.
enter image description here
1- Obviously this code sythesizes well, and simulation is OK. Then Implemented -> Assigned pins -> re-implemented -> and finally Generated .bit file ( this sequence: )
enter image description here
2- I also used the pins that don't require Vref. ( a:P3 , b:P4, out:P7). Here is a screenshot of pin assignment. At the end clicked Save:
enter image description here
3- Then I re-implemented and checked the pins in design summary. All OK:enter image description here
4- I have one of these Alkamar download cables. I connected the pins as recommended and ran iMPACT . It finds the device well and reads its config also well. I was happy when I saw "Program Succeeded " message! but when I connect VCCO voltage (3.3v) to P3(a) or P4(b), nothing happens in P7(out).I double checked everything but of no avail!
What is going wrong there?
enter image description here
Here is the schematic I use:
1- Test board:
enter image description here
2- Power Supply:
enter image description here
3- Crystal Oscillator part ( Not used in this test ):
enter image description here
This is the programming cable:
enter image description here
-
\$\begingroup\$ Is there anything to pull the pins low on your board? (pull down resistors, manual pull down with wires, etc.) \$\endgroup\$alex.forencich– alex.forencich2013年11月05日 15:46:17 +00:00Commented Nov 5, 2013 at 15:46
-
\$\begingroup\$ @alex.forencich No. Should I have them for XOR gate? \$\endgroup\$Aug– Aug2013年11月05日 15:47:26 +00:00Commented Nov 5, 2013 at 15:47
-
\$\begingroup\$ Is it correct, you didn't connect Vcco until after you programmed the part? That is not a good procedure. You should apply all of the Vcc's. Then program the part. \$\endgroup\$The Photon– The Photon2013年11月05日 16:10:15 +00:00Commented Nov 5, 2013 at 16:10
-
\$\begingroup\$ @ThePhoton . No I connected all VCCOs and VCCINTs BEFORE programming. without that iMPACT shows an error : "Cable Not Found" \$\endgroup\$Aug– Aug2013年11月05日 16:14:24 +00:00Commented Nov 5, 2013 at 16:14
-
1\$\begingroup\$ You should probably have pull-ups/downs on M0, M1, M2, PROGRAM, INIT, CCLK, TMS, and TCK (and maybe some I forgot) to make sure the device doesn't re-enter programming mode when it should be running normally. \$\endgroup\$The Photon– The Photon2013年11月05日 16:29:55 +00:00Commented Nov 5, 2013 at 16:29
2 Answers 2
This is an SRAM-based FPGA. After cycling power, its configuration is lost!
Normally a board using these FPGAs will have some non-volatile memory, and you load the configuration into that. The FPGA has some logic (configured by M0,M1,M2 the Configuration Mode pins) to boot itself from several common types of Flash memory or EEPROM. Some of them fit into the JTAG chain so you can program them with Impact and the Platform Cable you have.
I can't help with the precise details, the XC2S100 is a rather old device, but Xilinx have plenty of documentation on configuration memory.
Meanwhile, you can continue your experiments configuring the FPGA directly, in the knowledge that this is the normal behaviour for this FPGA.
This may seem odd, and there are indeed a few non-volatile FPGAs; ACTEL (Microsemi) make some. But SRAM technology is such a good match for FPGA logic that it makes sense despite the obvious drawbacks.
The non-volatile FPGAs are a compromise : relatively small and relatively slow - so much so that for most applications, the inconvenience of an an external ROM is a small price to pay for the advantages of SRAM-based FPGAs.
-
\$\begingroup\$ Thanks! what about XC3S400 ( I have one of that also)? \$\endgroup\$Aug– Aug2013年11月05日 20:49:23 +00:00Commented Nov 5, 2013 at 20:49
-
\$\begingroup\$ AFAIK anything that Xilinx (or Altera or Lattice) sells as an FPGA will have volatile configuration memory. Their CPLD's have nonvolatile configuration. \$\endgroup\$The Photon– The Photon2013年11月05日 21:44:09 +00:00Commented Nov 5, 2013 at 21:44
-
1\$\begingroup\$ XC3S400 too. There is a series(XC3S...AN series, not XC3S...A) with non-volatile memory in the same package (or on the same die, not sure which). The FPGA itself is still SRAM based;it loads itself from internal ROM on power up. \$\endgroup\$user16324– user163242013年11月06日 08:53:36 +00:00Commented Nov 6, 2013 at 8:53
-
\$\begingroup\$ Use the Spartan3AN series if you want non-volatile memory on the FPGA in the same package. It offers an SPI PROM with an in-built controller which you can use for bit-file storage. Upon power-up, the FPGA boots itself from the SPI PROM. For this code, you can use a small XC3S200AN device. Please note that Xilinx has removed support for other Spartan3 series devices in their latest versions of tools. \$\endgroup\$Avin– Avin2013年12月30日 12:31:53 +00:00Commented Dec 30, 2013 at 12:31
It sounds like you are not providing your inputs correctly. You say you apply VCCO to your two input pins to provide logic '1'. You can't just leave them unconnected for a logic '0' though. You must drive them either high (VCCO) or low (GND).