Part select in verilog

Question

I am a bit confused because of a odd situation in part select operator in verilog. I had read about part select and vector part select operators. But there is a situation where I am having variable[0:0], as part select, though it can be written as variable[0], and I think both are correct. Please correct me if I am wrong.

Using the earlier convention means variable[0:0], I am getting segmentation fault in my program. So I just want to confirm that using this type of convention is ok to use or not?

Answer 1

Using the convention variable[expr1:expr2] is correct as long as expr1 and expr2 are constant expressions. The defined range can be little endian, big endian or have expr1 = expr2 as in the case variable[0:0]. Although variable[0:0] is less readable than variable[0].

If your synthesis tool, simulator, etc. is crashing when you use this convention, it is not because you are using bad syntax, but because the tool has a bug in it. Tools are expected to give at least an error and a line number for unsupported code. A seg fault is not expected behavior. You should submit a bug report to the developer and either change tools or remodel your code so it does not crash the tool.