How to connect Verilog module's output to several wires?

Question

Say I have a module foo(in1,in2,out); and module mad1(in,out); module mad2(in,out); module mad3(in,out); While instantiating these modules I want to use the output (out) of foo as an input to each of the mad modules. Something like this:

input in1,in2;
output out1,out2,out3;
wire w_out;
foo i_foo(.in1(in1),.in2(in2),.out(w_out));
mad1 i_mad1(,in(w_out),.out(out1));
mad2 i_mad2(,in(w_out),.out(out2));
mad3 i_mad3(,in(w_out),.out(out3));

Is that approach correct or should I save the output of the foo module to a register?

Answer 1

This approach is perfectly correct.