Read and write values in Multidimensional arrays in verilog

Question

How can we read and write values in a multidimensional array in verilog, i had read in this link regarding different operations that can be done on multidimensional array. like if there is a part of code like this

input [15:0] me;
reg [15:0] p_array [7:0];
reg abc_pqr [2:0];
abc_pqr[0] <= me[0];
abc_pqr[1] <= me[1];
abc_pqr[2] <= me[1];
p_array[abc_pqr[0]] <= me[0];
p_array[abc_pqr[1]] <= me[1];
p_array[abc_pqr[2]] <= me[2];

so is this code will work and will not produce any error?

What is the difference between these two while assigning value

"<=" and "=", i had seen "<=" in most of the places during passing values.

Answer 1

This is not one question but breaking down the main points:

<= is a non-blocking assignment used when implying a flip-flop output.
= is a blocking assignment used when implementing combinatorial output.

example usage:

input [10:0] in_data;
reg [11:0] flip_flop;
reg [11:0] next_data
//Flip-flop
always @(posedge clock) begin
 flip_flop <= next_data;
end
//Combinatorial
always @* begin
 next_data = in_data + 11'd1;
end 

You defined 3 different data types:

input [15:0] me;
reg [15:0] p_array [7:0];
reg abc_pqr [2:0]; //Same as reg [0:0] abc_pqr [2:0]

me is a standard 16 bit word. p_array is an 8 deep memory of 16 bit words.
NB: it is typical to define as reg [15:0] p_array [0:7]; abc_pqr [2:0]; is a 3 deep 1bit memory.

You have :

abc_pqr[0] <= me[0]; //This is a 1 bit assignment:
abc_pqr[1] <= me[1];
abc_pqr[2] <= me[2]; //<-- corrected this to 2

Looks valid.

Then :

p_array[abc_pqr[0]] <= me[0];

p_array needs a [7:0] wide index, you have only supplied 1 bit. and a p_array element is 16 bits wide your left hand side is again only 1 bit.

• doug65536: Ok... but what if I declared the array correctly as an array of 16 bit regs and I want to access the low two bits of the 0th entry. Would it be p_array[0][1:0] <= 2'b11; ? I can't get that to work.
• pre_randomize: @doug65536 if you would like to write a question with what you are trying to do and what you have tried then we can have a go at answering it, link back to here if you want to provide more context. NB i think Stackoverflow is the better place for Verilog programming questions.