ModelSim: Non-Synthesizable Verilog Reference

Question

Where would I find a good reference (or even cheat sheet) on the non-synthesizable functions/syntax/commands that can be used in Verilog with ModelSim?

In other words, where would I find a complete reference that lists $strobe, $display, # and similar statements?

I seem to be able find bits and pieces about System Tasks and Assertions on Google, but I'd like to find a complete resource if possible.

Answer 1

Perhaps what you need is in IEEE Standard 1800:2023 SystemVerilog— Unified Hardware Design, Specification, and Verification Language, available for free by signing up to IEEE "GET" programme

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Answer 2

Section 21 IEEE 1800-2023 SystemVerilog LRM

Answer 3

The previous answers correctly point to the current version of the IEEE Std as the ultimate reference.

Note also that there is a link to the Std in the system-verilog tag info.

that can be used in Verilog with ModelSim

It is also important to note that, while all simulators strive to comply with the Std, they sometimes fall short. In the best case, the simulator tool documentation would itemize known discrepancies. But, more likely than not, simulators will generate syntax errors when compiling code that is not yet implemented.