I'd like to trigger a GPIO when detecting a falling edge on my PWM.
I want to do all of this within the same timer.
For example:
Timer 1: PWM Generation
Timer 2: Input capture indirect mode or something that would allow me to detect the falling edge.
I want to do it fully in software (no hardware wire between channel 1 and channel 2' GPIOs and just use a simple input capture).
I'm using a NUCLEO-H753ZI.
Thanks
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\$\begingroup\$ Why are you not triggering the PWM interrupt on any edge you want? \$\endgroup\$Justme– Justme2024年12月15日 22:07:31 +00:00Commented Dec 15, 2024 at 22:07
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\$\begingroup\$ @Justme I'm starting to learn trigger modes and whatnot, can you elaborate further? \$\endgroup\$B.Adlane– B.Adlane2024年12月16日 07:18:01 +00:00Commented Dec 16, 2024 at 7:18
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\$\begingroup\$ What exactly do you want to trigger ? Do you want to trigger one timer by event from another timer ? \$\endgroup\$Michal Dudka– Michal Dudka2024年12月16日 07:57:13 +00:00Commented Dec 16, 2024 at 7:57
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\$\begingroup\$ @MichalDudka I want to trigger a GPIO toggle at every falling edge of my PWM, i can't use multiple timers, i have to use a single timer for that \$\endgroup\$B.Adlane– B.Adlane2024年12月16日 08:20:34 +00:00Commented Dec 16, 2024 at 8:20
1 Answer 1
Based on the comments to the original question I assume that you generate PWM and you need to toggle some GPIO at the same time when you PWM signal goes low (falling edge). It is pretty simple. Select timer with two or more outputs (for example TIM3). Let him generate PWM on one channel (exactly "PWM edge-aligned mode"). Then value in compare register define "compare event" - moment when PWM goes low (your falling edge). Configure second channel in "output compare toggle mode" and write the same value in its compare register. When counter reaches value in this compare register(s) it toggles timer output. Then your falling edge and toggle will be generated at exactly same time.
When you need to change duty cycle, you have to write new value into two compare registers (one controlling PWM, second controllig toggle, both need the same value). Because there is a risk of a race condition, you should to activate "update disable" feature (UDIS bit in TIM3.CCR). Then write both values into compare registers and then clear "update disable". Of course both channels should have buffer enabled (as is usual with PWM).
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