STM32 timer PWM input capture and reset in slave mode (SPL)

Question

Could someone explain how PWM capture mode employs the Timer's Master-Slave mechanism? The example sets up input capture on Channel 2 but does not explain how IC1 is configured implicitly to capture the falling edge.

I am especially interested in these three SPL functions:

 /* Select the TIM3 Input Trigger: TI2FP2 */
 TIM_SelectInputTrigger(TIM3, TIM_TS_TI2FP2);
 /* Select the slave Mode: Reset Mode */
 TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Reset);
 /* Enable the Master/Slave Mode */
 TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);

implemented in stm32f10x_tim.c. They all write to TIMx->SMCR.

According the diagram from UM0008 rev 14 (rev 16) ...

ST UM0008 rev. 14 Figure 100. General-purpose timer block diagram

... TI2FP2 is not even connected to IC1, that would be TI2FP1. So I can understand that these commands configure the reset. But what causes IC1 to capture?

• handle: Note that in UM0008 section "15.3.6 PWM input mode" suggests that both capture units be configured, which the example does not do.

Answer 1

It just caught my eye that the PWM_Input example uses TIM_PWMIConfig() instead of TIM_ICInit() as the InputCapture example does. This is where the missing part is happening: it also configures the other input capture channel. Note that the automatic reset apparently only works for channels 1&2, not 3&4, as their signal is not connected to the "Slave mode controller".