Quartus FPGA critical path using timing report

Question

I'm trying to understand how Quartus works to compile your design when you give it a time constraint (specifying clock period on .sdc file).

To find the critical path of my design using Quartus, why do I have to set the clock period such that there's minimum slack? As I change the clock period, why do the delays of each path change? What is actually happening to my compiled design when I change the clock period?

Answer 1

Quartus by default uses timing driven synthesis and fitting. What that means is that if the timing constraints are easy to meet, it will spend less time optimising the design and less time trying to find an optimal fit.

That means that if you lower the frequency in the timing constraints, then rerun the synthesis, it's likely you'll end up with a lower performing design - because meeting timing is good enough, no point it working harder than necessary to do that. You'll also notice the time spent running the tools reduces too.

Conversely if you make the timing constraints harder to meet, the tools will work harder and harder to try and accomplish the goal, eventually failing to do so, which is where you start getting negative slack values.

• A negative setup slack means the delay from one register to the next is longer than the clock period (less any clock skew), which is sensitive to routing delays and process/temperature variations, hence measured on multiple timing corners.

• A negative hold slack implies the signal changed too close to the clock edge, which is usually automatically fixed by the tools by increasing the routing length as long as there is enough setup slack and space to allow it.

If you want to find the worst case path in the design, you'll want to use the TimeQuest tools. You can run TimeQuest GUI from within Quartus which will allow you to amongst other things see details about the slowest paths in the design (path with least positive or most negative slack). You can also extract FMax information from this tool also no need to change the constraints.

Bare in mind though that even tiny changes to the constraints or logic can wildly affect the timing performance in unpredictable ways as the fitter is essentially playing a massive game of whack-a-mole. So the slowest path may change each time, but you should get a sense with a bit of practice of which region of the design required work to either meet or improve timing.

• Simon Richter: Also, there is an option to randomize the starting conditions for the optimizer. If that is enabled, two consecutive runs will end up with wildly different timings, that has taken many people by surprise. For a design that is teetering on edge, that can be the deciding factor between pass/fail, but the results are not reproducible unless you generate and manage the random seed outside the synthesis process.
• Tom Carpenter: @SimonRichter Interesting, do you remember which option that is? From my experience Quartus seems to produce reproducable results if compiled in the same version from the same design files. There is a fitter seed parameter which is used to select the starting seed for the "psuedo-random" process, but as long as you don't change that value it stays consistent. In fact changing that starting seed by a small amount (e.g. change 72 to 73) can be very useful for improving timing as it doesn't actually seem to wildly change the results, only slightly tweaks them compared with a large change in seed.
• Tom Carpenter: (I'm using 22.1 currently, but was the same in 17.1)
• Simon Richter: exactly this one -- this can also be set to generate a new random number every time, and I've seen it activated in quite a few projects, where people were then confused about it.
• Tom Carpenter: @SimonRichter Ah I see, didn't know you could set it to be randomised, interesting.