doubt regarding class handle in system verilog

Question

I am unable to understand what actually the assignment smpl=e_smpl; does. I thought that by doing so sample class handle will also point to the ext_sample but it is not the case as smpl.print(); is invoking the task defined in sample class not the ext_smpl class. So what does smpl=e_smpl; actually does. How is it different from smpl=new();

class sample;
 int a;
 int b;
 task print();
 $display("printing from parent class");
 $display("a=%0d",a);
 $display("b=%0d",b);
 endtask
endclass
class ext_sample extends sample;
 task print();
 $display("printing from child class");
 $display("a=%0d",a);
 $display("b=%0d",b);
 endtask
endclass
module top;
 sample smpl;
 ext_sample e_smpl;
 initial begin
 
 e_smpl=new();
 smpl=e_smpl;
 
 smpl.a=10;
 smpl.b=20;
 
 smpl.print();
 e_smpl.print();
 
 end
endmodule

Answer 1

I recommend not using the terms child and parent when talking about class inheritance. Use base and derived. You are declaring two class types sample and ext_sample the latter inherits all of the declarations in sample. So ext_sample has two different print tasks declared.

The statement e_smpl=new(); constructs one class ext_sample object with the two print tasks and stores its handle in the class variable e_smpl. Inheritance lets you store a handle to an object in class variable on any base class type, but you will only be able to access the declarations defined by the base type.

This is a very complex topic and I suggest a few other resources:

https://blogs.sw.siemens.com/verificationhorizons/2013/07/16/class-on-classes/

https://verificationacademy.com/topics/systemverilog/systemverilog-oop-for-uvm-verification/