Can an event name be manipulated in Verilog/SystemVerilog?

Question

In a Verilog testbench.v, there are commands that are used in a task.

task cmd_script;
begin
...
event check1_e;
event check2_e;
..
integer cmd_file;
integer cmd_char;
reg [31:0] head_data;
reg [31:0] tail_data;
cmd_file = fopen("data.txt");
cmd_char = $fgetc(cmd_file);
while(cmd_char != EOF) begin
...
$fscanf(cmd_file, "%s\n", cmd);
case (cmd)
 TEST1 : begin
 end
 TEST2 : begin
 $fscan(cmd_file, "%h %h\n", head_data, tail_data);
 ->check1_e = head_data;
 end
 ...
end

Can I pass variable name as a string to an event, or can an event name can be manipulated?

• dave_59: It's not clear how you intend to use the events, or what you are expecting ` ->check1_e = head_data;` to do. Please expand your question with a little more description and code. There might be other way of coding this with an associative array of events
• Carter: @dave_59 Normally when using the Event syntax, I use event with "event variable name" and "->variable name". If a task receives a string-type argument, can I specify a variable name for the event depending on the name of the argument? The amount of arguments was too large to implement an event for each task's argument, so the question was whether we could pass the event by the argument's name.
• dave_59: Suppose head_data had the value 32'h5C8A8B42. How do you want your attempted statement ->check1_e = head_data; to behave? See xyproblem.info
• Carter: @dave_59 Suppose head_data has string type such as "str_here1", then I expected that event ->str_here1.
• dave_59: Then you should edit your example to show that. You wrote "reg [31:0] head_data;" you would need 72-bits to represent "str_here1" and you have no event named that

Answer 1

You can create an associative array of events map strings to events

event check1_e;
event check2_e;
...
event emap[string] = '{"check1_e":check1_e, "check2_e":check2_e, ...};

Then use this code to trigger

string head_data;
head_data = "check1_e"
if (emap.exists(head_data)) 
 ->emap[head_data];
else 
 $error("%s event does not exist",head_data);

Answer 2

No, it is not possible to assign a value to an event type in SystemVerilog that way.

The following is a syntax error:

 ->check1_e = head_data;

The following is proper usage of an event:

 ->check1_e;

That syntax is used to trigger an event which can be detected elsewhere in the code by waiting for the event using syntax such as the following:

 @(check1_e);

Events are used like a simple handshake, or communication between processes. They can not pass values.

Refer to IEEE Std 1800-2017, section 6.17 Event data type