Verilog sum problem

Question

I have an array named mixed_signal, and I need to sum of its elements in a register but it cannot be sequential. Can you help me?

wire signed [N-1:0] mixed_signal [8:0];
assign mixed_signal[0]=coeffs[0]*noisy_in;
generate
genvar j;
 for(j=1;j<tap;j=j+1)begin
 assign mixed_signal[j]= coeffs[j]*delayed_signal[j-1];
 end
endgenerate

All off the code is given below

module filter_fir(clk,rst, noisy_in,filtered_out
);
parameter N=16; // Size of the data
parameter tap=9;
input rst,clk;
input [N-1:0] noisy_in;
output reg [N-1:0] filtered_out;
reg [N-1:0] coeffs [tap-1:0];
wire signed [N-1:0] delayed_signal [8:0];
wire signed [N-1:0] mixed_signal [8:0];
wire signed [N-1:0] sum ;
initial begin
coeffs[0]=16'h04F6;
coeffs[1]=16'h0AE4;
coeffs[2]=16'h1089;
coeffs[3]=16'h1496;
coeffs[4]=16'h160F;
coeffs[5]=16'h1496;
coeffs[6]=16'h1089;
coeffs[7]=16'h0AE4;
coeffs[8]=16'h04F6;
end
ddf delay_call(.rst(rst),.clk(clk),.data_delayed(delayed_signal[0]),.data_in(noisy_in));
generate 
genvar i;
 for(i=0;i<(tap-1);i=i+1)begin 
 
 ddf delay_call(.rst(rst),.clk(clk),.data_delayed(delayed_signal[i+1]),.data_in(delayed_signal[i]));
 
 end
endgenerate
assign mixed_signal[0]=coeffs[0]*noisy_in;
generate
genvar j;
 for(j=1;j<tap;j=j+1)begin
 assign mixed_signal[j]= coeffs[j]*delayed_signal[j-1];
 end
endgenerate
//Here I need A combinational sum = sum + mixed_signal[j] 
//functionality, similar to C,
always@(posedge clk)begin
 
 filtered_out<=sum;
end 
endmodule
module ddf (rst,clk,data_in,data_delayed);
parameter N=16;
parameter tap=9;
input clk,rst;
input [N-1:0] data_in;
output reg [N-1:0] data_delayed;
always@(posedge clk)begin
 if(rst) data_delayed<=0;
 else data_delayed<=data_in;
end 
endmodule

• elysee: @toolic The problem is that I need sum = sum + mixed_signal[j] functionality, similar to C, but in RTL, I understand that I can't directly connect the input to the output. Is there a solution for this? (mixed_signal is multidimensional array)

Answer 1

If you need to generate the sum in combinitorial, you can modify mixed_signal to be the partial sum of all lesser signals:

wire signed [N-1:0] mixed_signal [8:0];
wire signed [N-1:0] sum;
assign mixed_signal[0]=coeffs[0]*noisy_in;
generate
genvar j;
 for(j=1;j<tap;j=j+1)begin
 assign mixed_signal[j]= mixed_signal[j-1] + coeffs[j]*delayed_signal[j-1];
 end
endgenerate
assign sum = mixed_signal[tap - 1];

Answer 2

This is a pretty standard way to sum up the values of an array in Verilog:

reg signed [N-1:0] sum;
// ...
integer s;
always @* begin
 sum = 0;
 for (s=0; s<tap; s=s+1) begin
 sum = sum + mixed_signal[s];
 end
end

Note that sum is now a reg instead of a wire.

You may need to increase the bit width of sum. Generally, the sum of 9 16-bit values requires more than 16 bits.

• elysee: Thanks for your answer. I already tried it but it connects input of the adder to the output of adder. That's why it cannot be implemented.
• toolic: @EmreYILDIZ: What software did you try it with? Simulation, synthesis, other? Edit your question with new information instead of here in the comments.