How to truncate an expression bit width in Verilog in 2023?

Question

I have the same question as here: How to truncate an expression bit width in Verilog?

But I was hoping that in 2023, there would be more interesting answers that in 2013!

My specific use-case:

localparam logic [31:0] BAR0_OFFSET_MASK = {32{1'b1}} << (10);

Some tools complains that LHS is 32 whereas RHS is 42, and I would like to select part of the result of the shift operation without creating a temporary variable or a function.

• Community: Please clarify your specific problem or provide additional details to highlight exactly what you need. As it's currently written, it's hard to tell exactly what you're asking.

Answer 1

Tools that complain that the RHS of the assignment width is 42 bits are incorrect. The width of a shift operation is determined by the width of its left operand.

Regardless, SystemVerilog added a select in a concatenation

localparam logic [31:0] BAR0_OFFSET_MASK = { {32{1'b1}} << (10) }[31:0];

You could also use casts

localparam logic [31:0] BAR0_OFFSET_MASK = 32'( 32'('1) << (10)) ;

• Bamban: Many thanks for the very fast answer! I won't name the tool that begins with Spy and finish with drink... Great to see that the language advanced.