Why I am getting one clock cycle delay in Verilog case statement?

Question

I have a Verilog code here:

module VendingMachine(
 input clk,
 input reset,
 input [1:0] coins ,
 output reg serving,
 output reg [1:0] state
 );
 parameter [1:0] WAIT = 3'b10;
 parameter [1:0] READY = 3'b01;
 parameter [1:0] SERVE = 3'b11;
 
 always @(posedge clk or posedge reset)
 begin
 if (reset) 
 begin 
 state <= READY;
 serving <= 0;
 end 
 else
 begin
 case(state)
 READY: begin
 if (coins == 10) 
 state <= SERVE;
 else if (coins == 01)
 state <= WAIT;
 end
 WAIT: begin 
 if (coins == 01 || coins == 10) 
 state <= SERVE;
 else 
 state <= WAIT;
 end
 SERVE: begin 
 serving <= 1;
 state <= READY;
 end
 default: state <= WAIT;
 endcase
 end 
end 
endmodule

The output of the run is as follows:

0 clock=0 coins=xx state=01 serving=0
50 clock=1 coins=xx state=01 serving=0
100 clock=0 coins=xx state=01 serving=0
150 clock=1 coins=xx state=01 serving=0
200 clock=0 coins=01 state=01 serving=0
250 clock=1 coins=01 state=10 serving=0
300 clock=0 coins=01 state=10 serving=0
350 clock=1 coins=01 state=11 serving=0
400 clock=0 coins=01 state=11 serving=0
450 clock=1 coins=01 state=01 serving=1
500 clock=0 coins=01 state=01 serving=1

I was expecting to get the value of serving to change from zero to one when the value of state changed from 10 to 11, but there seems to be one complete clock cycle delay before the value of serving changes.

Answer 1

At the positive edge of clk you change from WAIT state to SERVE state. You don't change the serving signal.

On the next clock cycle whilst in SERVE state, you change the serving signal to 1.

Notice how these two things happen in different clock periods? Essentially the value of the state machine itself always changes one clock before anything in the corresponding case statement happens.

---

As an aside you've written coins == 10 (decimal 10), instead of coins == 2'b10 (two bit binary number 10, decimal 2). This works by sheer chance, as decimal 10 truncated to two bits equals 2.

Answer 2

The other answer directly answers your question about the relative timing of your output signals, and it also provides an astute observation of a probable bug in your code (10 vs. 2'b10).

I also see another probable bug in the code. The serving signal can only go back to 0 when you asynchronously reset the state machine. I think you want to set serving to 0 in these states as well: READY and WAIT. Otherwise, it remains high regardless of how you change the coins input.