Defining vector in Verilog

Question

Given the following code:

module add16 (input [15:0] a,b, output[15:0] sum, output court);

Are both input a and input b 16 bits long, or is only input a 16 bits long?

• mendax1234: After digging deep into Verilog, I mean seeing more Verilog examples. I think this question is obvious, both input a and input b are 16 bits. However, is this just a coding convention?

Answer 1

The format is:

<direction> <type> [<packed size] list,of,var,names

The same principle applies to all variables.

So in your example as b has no direction/type/size definitions, it will take the same definitions as the port that came before it, a, hence both should be the same size and direction.

Personally I avoid this syntax an prefer to specify each ports direction, type and size individually. I find it clearer and avoids any ambiguity.

Answer 2

Until you specify a direction, a parameter "inherits" its size and direction from the previous one.

Re-write the module definition:

module add16 (
 input [15:0] a, b,
 output [15:0] sum,
 output carryout
);

Should be clearer now.

Here b "inherits" its direction and size from a.

If you wrote output [15:0] sum, carryout the carryout would be 16-bit long. But defining another direction with output allowed you to specify a size, 1-bit in this case.

• mendax1234: Thanks! So, in this example, the output is the direction and the type is omitted.
• Rohat Kılıç: @mendax1234 the output is direction, yes. For type, you normally don't have to specify a type for module inputs i.e. it's already in "bits" and you specify the size only. So the syntax is dir [MSB:LSB] var_name.
• Tom Carpenter: @mendax1234 when a direction is given, type is assumed to be wire. For outputs you can also have output reg.
• mendax1234: @TomCarpenter Okok. So, what's the difference between output reg and output wire? I know that if I want to assign the output value in an always block, it needs to be a reg and it can't be the wire. Are there any other differences?
• Tom Carpenter: @mendax1234 That's the only difference, the reg type can be assigned in a procedural block.