How can I fix the combinatorial loop alert in Vivado?

Question

always @ (state, count)
 begin
 if(st_rst == 1'b1)
 begin
 state <= 3'b101;
 count <= 0;
 end
 else
 begin
 state <= next_state;
 count <= count + 1;
 end
 case(state) 
 3'b101://reset & initialize
 begin
 mem_rst =1'b1;
 dis_rst =1'b1; 
 pe_rst = 1'b1;
 three_rst = 1'b1;
 two_rst = 1'b1; 
 next_state = 0;
 two_end = 1'b0;
 s_end_1 = 1'b0;
 s_end_2= 1'b0;
 s_end_3 = 1'b0;
 s_end_4 = 1'b0;
 
 s3_end_22 = 1'b0;
 s3_end_21 = 1'b0;
 s3_end_12 = 1'b0;
 s3_end_11 = 1'b0;
 en_dis = 1'b0;
 //etc...
 end

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is cont/st_rst_0. Please evaluate your design. The cells in the loop are: cont/s3_end_22_reg_i_4.

This is my part of my code, and the combinational loop occurred due to always @ (state, count).

I want to make controls when the count and state values change. How can I change it?

Answer 1

In the abbreviated code sample you show, this line is the cause of the combinational loop message:

 count <= count + 1;

The following line infers combinational logic:

always @ (state, count)

You should create another always block for your counter. For example, this infers sequential logic (not combinational logic):

always @ (posedge clk or posedge st_rst) begin
 if (st_rst) begin
 count <= 0;
 end else bgein
 count <= count + 1;
 end
end

You should remove count from your other always block.

This means that you also need to add a clock signal to your design (clk), if you don't already have one.

You should also separate the state logic into another sequential always block. Using several always blocks is a good practice to partition your logic; it often results in code which is easier to understand and maintain than trying to place all your code into a single block.

Also, it is better to use the implicit sensitivity list for combinational logic instead of explicitly adding signals (like state) to the list. Change:

always @ (state, count)

to:

always @*