VHDL procedure evaluation and call sequence

Question

I want to ask what is the order of procedure call in VHDL.

Below I have VHDL code showing a procedure called 'IncrementWrap' and a process which calls the procedure multiple times.

I got the code form a Youtube video and of course have not run it myself, but will this code even execute?

When the Tick value is = clock_frequency-1 just before the rising edge, the tick value gets reset back to 0 as shown by the procedure. But what about the conditional check beneath it? Will that also be evaluated? And the procedure 'IncrementWrap' called but for seconds?

Is the procedure and the conditional check beneath it evaluated in parallel?

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Answer 1

Looks like you are not aware of when a signal is updated inside a clocked process in VHDL.

In your code, the procedure IncrementWrap () will execute and update the respective signals if the preceding condition is true, and the update is not 'immediate'. The signals are updated after a delta delay by the simulator, i.e., the signals are scheduled to be updated only at the end of the execution of process (Clk) at the rising edge of Clk.

When the Tick value is = clock_frequency-1 just before the rising edge, the tick value gets reset back to 0 as shown by the procedure. But what about the conditional check beneath it?

Since the if condition goes true at the rising edge of Clk, Ticks is scheduled to be updated to 0 by the IncrementWrap() only at the end of process (Clk) execution. Hence, Ticks would still be ClockFrequencyHz-1 for the below statements to evaluate, for the current rising edge of Clk.

Answer 2

The effect of a sequential signal assignment in VHDL is not visible until the process ends. Procedures are irrelevant to this rule and behave as any other code in a process (the end of a procedure does not make any sequential effects become visible).

So, yes, your conditional will be hit even though the preceding procedure call sets the variable to 0.

• user16324: Until the process ends, or reaches a "wait".