I have usually seen VHDL keyword null being used in the others part VHDL case blocks. However, it also sometimes appears in else part of if statements. Unlike Python that requires us to use the keyword pass, I don't think VHDL has any such requirements.
On the other hand, I heard someone tell me once that the reason he uses the keyword null in the else part of VHDL if blocks is to prevent warnings from synthesis tools. I am personally not sure what he was talking about.
Is it important to use keyword null in VHDL for synthesis although it seems redundant and does not do anything? When do we actually need it in modern VHDL?
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\$\begingroup\$ TL/DR : Documentation. See stackoverflow.com/questions/42876613/null-statement-in-vhdl and electronics.stackexchange.com/questions/379822/… \$\endgroup\$user16324– user163242021年08月02日 18:49:56 +00:00Commented Aug 2, 2021 at 18:49
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\$\begingroup\$ Simply an explicit way of describing "do nothing and I mean it". You don't need to use null in codes otherwise. \$\endgroup\$Mitu Raj– Mitu Raj2021年08月02日 18:51:46 +00:00Commented Aug 2, 2021 at 18:51
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\$\begingroup\$ It is VHDL's equivalent to, "This page intentionally left blank". This ensures that people who maintain the code in the future do not worry that something was accidentally deleted. \$\endgroup\$Jim Lewis– Jim Lewis2021年08月02日 19:03:35 +00:00Commented Aug 2, 2021 at 19:03
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I have been programming in VHDL for 12 years, and I have never found the use of null to be a requirement. There may be some older tools out there that require it, but I have yet to come across one.
null can be used to make your code more readable by explicitly stating that a certain condition doesn't do anything.