How can I program flash using Vitis?

Question

I'm little new to Vitis and vivado. I have used ISE tools mostly for spartan 6 and it is steep learning curve for new tools.

I used iMPACT before with ISE to program flash using JTAG. Now with Vivado and vitis things are become more confusing for me.

What is real difference if I program flash using vivado and vitis ? I dont really get it. I know vitis has BSP bitstream and Vivado is just a hardware bitstream. When I use vitis "program flash" option then I can program the flash successfully but, after power cycle FPGA doesn't load config from the flash sit idle. I'm using CMOD S7 XCS725 and 2020.2 version.

Answer 1

So I finally figured it out. I positing it here for anyone who struggling with this. Vitis is not a great tool to do flash programming.

1. Create a block design with Microblaze (guide on how to do this here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi)
2. Add in the QSPI flash IP from the Board tab to the block design (usually 50 MHz clock to the external SPI clock on the AXI Quad SPI IP). Confirm that the IP confirmation on the AXI Quad IP is set to SPI Quad mode and the Slave Device is set to Macronix (presuming you have a rev B of the Cmod S7).
3. Finish generating the block design, create the HDL wrapper, and generate the bitstream (or only go through implementation).
4. Open the implemented design, so you can then go Project settings.
5. In the Project settings in the Bitstream section, set it so that the .bin file is created, go into the additional bitstream settings, set the Bitstream compression to True, set the configuration rate from 3 MHz to 33 MHz, and under Configuration Modes choose Master SPI x4. Click Ok and save the design.
6. Generate the bitsteam and export the .xsa and open Vitis.
7. Create a normal C application project (not SREC) and build the project. This will generate a .elf file.
8. Go back into Vivado, add that newly generated .elf file as a design source to the project and save (you'll probably be asked to save a new .xdc).
9. Right click on the Microblaze IP and associate that .elf under the Design sources (as opposed to simulation sources). Regenerate the bitstream.
10. Open up the hardware manager, click Add Configuration Memory Device (Macronix part number MX25L3233F for Cmod S7-25 Rev B), and program it with the .bin file.

You'll need to power cycle the board (I just unplugged and then replugged the S7 via USB) but the flash memory Microblaze program should be loaded and running.

• thomas.cloud: Thank you for posting this! I have also added an answer, but it is only as a follow on to your answer with a couple more details.

Answer 2

As long you want to program the flash for a "normal" FPGA (no ARM SoC or other soft-cpus) the procedure is simple and it is indifferent if you do so using vitis or vivado directly. But just to be precise note that the BSP (Board Support Package) you mention is not a configuration bitstream.

To program the flash using vivado you can follow the procedure defined in ug908 at chapter 6. In short you will have to:

1. Define the memory device (in your case Macronix MX25L3233F according to the manual): tools>add configuration memory device.
2. generate a configuration file with the bitstream (the bitstream has format .bit, the flash conf file either .mcs or .bit), and then flash it on the device: tools>generate memory configuration file
3. Flash it on the device.

I would also suggest to take note of the commands being executed on the "Tcl console" window; you can write them down in a TCL script to script the whole procedure (and maybe put everything in a Make script).

• Manny: I can program the flash but nothing happens when I power cycle. I have the program (without configuration) worked well before. The flash boot writing address is 0x00000000 and offset is FLASH_IMAGE_BASEADDR 0x00140000. I don't know if this offset number is write. I checked the memory (flash - MX25L3233F) Configuration Memory information: File Format BIN Interface SPIX4 Size 32M Start Address 0x00000000 End Address 0x01FFFFFF Addr1 Addr2 0x00000000 0x0012F2CB Jul 30 example/microblaze_example.runs/impl_1/design_1_wrapper.bit
• J.W.: could you clarify where you are inserting those parameters? I am curious about this write offset in particular; there should be no reason in this case to write the bitstream at an offset different from 0. Also try to verify the flash after the write, and just to be sure try to execute the command "Boot from Configuration Memory Device" as shown in pag 59 of ug908.

Answer 3

I just wanted to provide a few more details on top of Manny's great answer.

2 (from Manny answer). I don't think this step is necessary. I did it both ways, with and without this step. Step #10 seems to take care of programming the Flash, and this is reinforced by the Basys 3 documentation which says:

Basys 3 description of flashing procedure

Here is the layout from MicroBlaze to the Flash Qspi ports. I added a custom Vhdl module to map from the axi_quad_spi Ip to the Qspi vector. Here is the module for the mapping:

library IEEE;
use IEEE.std_logic_1164.all;
-- Consolidate the the Axi Quad Spi output to a vector
-- so it can be connected to the QspiDB[3:0] vector.
entity Basys3QspiPinToVector is
Port ( 
 
 QspiBit0 : in std_logic;
 QspiBit1 : in std_logic;
 QspiBit2 : in std_logic;
 QspiBit3 : in std_logic;
 
 QspiDB : out std_logic_vector (3 downto 0)
);
 
end Basys3QspiPinToVector;
architecture Behavior of Basys3QspiPinToVector is
begin
 QspiDB <= QspiBit3 & QspiBit2 & QspiBit1 & QspiBit0;
end Behavior;

I guess this connection might be nice if wanting use the Flash as a storage device during program use.

Layout from MicroBlaze to Flash Qspi ports

8 (from Manny answer). Do not include the .elf file in the Vivado source directory. Make sure to uncheck the box that requests to include the file, so that each subsequent build in Vitis will be looking at the most recent .elf file.

9 (from Manny answer). Regenerate the bit stream each time the .elf file is updated. Even if it says the bitstream is up-to-date, regenerate or you can get stale copies of the .elf file.